• State
  • Locked Locked
  • Replies 8 replies
  • Subscribers 100 subscribers
  • Views 257 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

AM68A: AM68A CPLD design document for illustrating how to use it?

Rio Chan
Genius 14625 points
Part Number: AM68A

Champs:

#1.

In the AM68A design files, customer is asking where to get the CPLD detail documents? How to use and program it?

#2. 

In the file: PROC125E2_CPLD_CODE.v, how to set those boot mode pins in the code? 

What's the mapping of this file and correspondent to the AM68A SK- EVM schematic?

input i_soc_porz_out,
input i_gpio_rgmii_rst,
input i_gpio_pcie1_m2_rstz,
input i_sys_pwr_pg,
input i_pb_porz,
input i_ta_porz,
input i_jtag_resetz,
input i_ta_resetz,
input i_resetstatz

BR Rio

  • 0
    TI__Guru 50193 points

    Hi Rio,

    I would need to check with the hardware team, but my assumption is CPLD is usually untouched since this is used for boot modes. Is there a reason for customer wanting to program CPLD?

    As for which signal is mapped in the schematic, I would recommend looking at RESET/BOOTMODE LOGIC section of PROC125E1 or 2. Below should be the signal going into the CPLD:

    Regards,

    Takuma

  • 0 in reply to Takuma Fujiwara
    Prodigy 40 points

    Hi Takuma,

    Is the i_soc_porz_out routed out of the CPLD? This signal is not mapped in the schematic. Do you have the pin mapping file for the CPLD?

    Thanks.

    Best regards,

    Chee Weng 

  • 0 in reply to Wong Weng
    TI__Guru 50193 points

    Hi Wong,

    I think this i_soc_porz_out is CPLD_PORz_UNUSED.

    The main reasoning being that this is the only PORz signal on the schematic that does not map to any signals in CPLD source code.

    Unfortunately, the hardware engineers that could confirm this assumption is currently on break and would not be back until the second week of January.

    Regards,

    Takuma

  • 0 in reply to Takuma Fujiwara
    Prodigy 40 points

    Hi Takuma,

    In the schematic, CPLD_PORz_UNUSED is no connection net. Hence, I need the CPLD mapping file to understand the implementation.

    Regards,

    Chee Weng

  • 0 in reply to Wong Weng
    TI__Guru 50193 points

    Hi Weng,

    I will check with our team if we have a "CPLD mapping file". To my knowledge, I have not seen said file. However, to set expectations this request will most likely be fulfilled after New Years due to availability of our team members.

    Apologies for the inconvenience, and thank you for your patience.

    Regards,

    Takuma

  • 0 in reply to Takuma Fujiwara
    Prodigy 40 points

    Hi Takuma,

    Thanks, I will wait till your team is back from holiday for the CPLD issue.

    I have another query. I wonder whether AM68A can support a USB3.0 Hub and an DRP(OTG) USB port. By the way, does AM68A support two USB port? Please advise.

    Thanks.

    Regards,

    Chee Weng

  • 0 in reply to Wong Weng
    Prodigy 40 points

    Hi Takuma,

    To support USB device firmware upgrade, my design needs one USB (DRD mode) port. In addition, my design needs a USB 3.0 hub to provide an addition 4 USB ports.

    Can AM68A support the above requirement? Please advise.

    Best regards,

    Chee Weng

  • 0 in reply to Wong Weng
    TI__Guru 51575 points

    I too do not have the CPLD mapping file.  I believe the i_soc_porz_out is sourced from MCU_PORz_3V3 (pin 43).

    AM68A supports a single USB interface, so if supporting HUB...would need a mux (or similar logic) to support DRD mode for firmware upgrade.