TMS320C6657: TMS320C6657

Doron,

Sure.... Let me look at it and get back.

Regards

Shankari G

//***************************************************************************
// Function:   SerialPortSWI
// Type:       Void
// 
// Purpose:    This function is a software interrupt service routine
//             This function called by hardware interrupt service routine.    
//             Optimized by Gilad Z.
// 
// Inputs:     NONE
// Outputs:    NONE
// 
//***************************************************************************
#pragma CODE_SECTION(SerialPortSWI, "SerialPortSWI_Sect");    
Void SerialPortSWI(Void) 
{    
    S16                         i,k;     
    S16                         NumOfEntries;
    *(U32*)0x01848214 = 0;
    
    *(U32*)0x01848214 = 1;      

}

//***************************************************************************
// Function:   SerialPortHWI
// Type:       Void
// 
// Purpose:    This function is a hardware interrupt service routine.
//             It posts the software interrupt.
//                 
// 
// Inputs:     NONE
// Outputs:    NONE
// 
//***************************************************************************
//#pragma CODE_SECTION(SerialPortHWI, "IRAM");
void SerialPortHWI(void)
{
 
    System_printf ("Debug(Core %d): SerialPortHWI serviced\n", coreNum);

    Swi_post(SWI_SerialPort_Rx);

}

//#endif




void Mcbsp_interrupt_init(void)
{

    Hwi_Params      hwi_params;
    static Bool     port0Init   = FALSE;

    Bool            error_flag;

    if (!port0Init)
    {
        error_flag = FALSE;
        Hwi_Params_init (&hwi_params);

        /*
         * Setup TX Int using BIOS6 Hwi module
         */
        hwi_params.arg          = (UArg) 0;
        hwi_params.enableInt    = 1;
        hwi_params.eventId      = CIC0_OUT;   //EDMA3_CC_INT1; //APP_EMAC0_TX_INT_EV;
        hwi_params.maskSetting  = ti_sysbios_hal_Hwi_MaskingOption_SELF;

        if (Hwi_create (APP_MCBSP0_TXINT_ID, (ti_sysbios_hal_Hwi_FuncPtr) &SerialPortHWI, &hwi_params, NULL) == NULL)
        {
            error_flag = TRUE;
        }

        if(!error_flag)
        {
            port0Init = TRUE;
            edmaEnterSingleCoreCriticalSection(0);
        }
    }

}

/**
 *  @b Description
 *  @n
 *      The function is used to provide critical section to prevent access of shared
 *      resources from single core and multiple threads.
 *
 *  @param[in]  port_num
 *      EMAC port number which needs critical section to protect its resources.
 *
 *  @retval
 *      None
 */
void
edmaEnterSingleCoreCriticalSection
(
    Uint32      port_num
)
{
    IER &= ~APP_MCBSP0_INT_FLAG; 
}

void EnableMCBSPInterrupts(void)
{
	unsigned int	intState;

	/* Disabling the global interrupts */
	intState = Hwi_disable();

	/* route Ecc error event 110 (system event) at CIC0/1 to event (CIC0_OUT0 Or CIC1_OUT0) at cic0/1_out (host event)*/
	/* those CIC0/1_out are maped to event 102 at CorePac (broadcast event) [figure 7-32 at tms320c6678]*/
	//CpIntc_mapSysIntToHostInt(0, MCBSP_RXV_EVENT_ID, 0 /*CICO/1_OUT0*/);
	CpIntc_mapSysIntToHostInt(0, 32, 0 /*CICO/1_OUT0*/);

	//CpIntc_enableSysInt(0, MCBSP_RXV_EVENT_ID);
	CpIntc_enableSysInt(0, 32);

	CpIntc_enableHostInt(0, 0 /*CICO/1_OUT0*/);

	/* event 102 at CorePac is routed, and configured through the events combiner (Shannon.cfg)*/

	/* Restore interrupts */
	Hwi_restore(intState);

}

Doron,

Helping in the customized code development and debugging.... is beyond the scope of the E2E forum.

I hope you understand... as the scale of support is world wide and the bandwidth will be the concern.

--

In spite, if you think of setup that I have, in my EVM, no devices are connected through McBSP to check the interrupt portion of the code.

I could only theoretically check...

Regards

Shankari G

can you please provide sample use of MCBSP with interrupt (without the EDMA)

Doron,

Let me have a look of its availability....

Regards

Shankari G

Doron,

As per the functional block diagram of McBSP of C6657, the data transmission happens through the the EDMA transfer controllers.

So, the sample code is provided with EDMA.

"There is one EDMA Channel Controller on the C665x device: EDMA3_CC. It has four transfer controllers: TC0, TC1, TC2, and TC3. In the context of this document, TCx associated with CC is referred to as EDMA3_CC_TCx. Each of the transfer controllers has a direct connection to the switch fabric. Section 9.2 lists the peripherals that can be accessed by the transfer controllers."

The one among the list of peripherals is MCBSP.

For more info, please refer,

https://www.ti.com/lit/ds/symlink/tms320c6657.pdf section 9.1

https://www.ti.com/lit/ug/spruhh0/spruhh0.pdf section 1.3

Regards

Shankari G