[FAQ] AM62P / AM62P-Q1 Custom board hardware design – I2C interface

Hi Board designers, 

Refer below inputs for the I2C interface related queries.

1. Need information on the number of I2C interfaces available.

The device contains six multicontroller Inter-Integrated Circuit (I2C) controllers. Each I2C controller was designed to be compliant to the Philips I2C-bus specification version 2.1. However, the device IOs are not fully compliant to the I2C electrical specification.

Open Drain buffer type I2C interface - MCU_I2C0 and WKUP_I2C0

These I2C interfaces are Open drain type IOs. These I2C interfaces are fail-safe IO terminals.

The rise and fall times of the I2C signals connected to these ports must not exceed a slew rate of 0.8 V/ns (or 8E+7 V/s). This limit is more restrictive than the minimum fall time limits defined in the I2C specification. Therefore, it may be necessary to add additional capacitance (RC) to the I2C signals to slow the rise and fall times such that they do not exceed a slew rate of 0.8 V/ns.

Refer below 

Reference: AM62P SK schematics

Note: The board designers are responsible for implementing whatever precautions are necessary (required) to ensure their custom board design does not violate the requirements mentioned (specified) in the data sheet. The recommendations provided in the schematics design and review checklist or the SK schematics implementation can be used as a starting point.

LVCMOS buffer type I2C interface - I2C0, I2C1, I2C2, and I2C3

These I2C interfaces are LVCMOS IO types. LVCMOS IOs being used on these ports are connected such they emulate open-drain outputs.

2. Termination of I2C interfaces when used as I2C interface and not used as I2C interface.

Open Drain buffer type I2C interface - MCU_I2C0 and WKUP_I2C0

Refer Pin Connectivity Requirements in the datasheet.

These interfaces are recommended to be terminated when configured as I2C or as GPIO. When the IO is configured as input and being driven by a push-pull input from power-up the termination can be depopulated

LVCMOS buffer type I2C interface - I2C0, I2C1, I2C2, and I2C3

When configured as I2C interface, pullups are recommended. Since these IOs are LVCMOS type, the pullups are recommended to be connected with the shortest stub. When configured as GPIO, based on the use case an external pull can be provided or the internal pulls can be used.

3. Any additional recommendations / Guidelines

I2C3 has one or more signals which can be multiplexed to more than one pin. Timing is only valid for specific pin combinations known as IOSETs. Valid pin combinations or IOSETs for this interface are defined in the SysConfig-PinMux Tool.

Refer below section of the device specific datasheet.

7.8.1 I2C Open-Drain, and Fail-Safe (I2C OD FS) Electrical Characteristics

       4. Any concerns on Interfacing SoC Non-Failsafe I2C to devices that are powered before the SoC- Ex PMIC 

Are the attached PMIC IOs true open-drain I2C IOs?  If so, are the pull-up resistors associated with this I2C port powered by the same power supply that is used to power SoC I2C Example I2C0 IOs?  We should not have a fail-safe problem if the answer to both questions is yes.

 Is there anything else connected to these I2C signals that could source a potential to the I2C0 pins before the IOs are powered? 

We are only concerned with fail-safe if there is a possibility for the attached devices to apply a potential to the SoC IOs before they receive power.  We do not have any fail-safe concern if that is not possible.

      5. Any exception that are required to be considered when using the I2C interfaces. 

Refer section 6.11.5.13 I2C of the data sheet.

Read through the Exceptions section for I2C0, I2C1, I2C2, and I2C3 + Exceptions section for MCU_I2C0 and WKUP_I2C0

     6. Can the I2C interface be used to interface with devices supporting SMBus or PMBus 

The I2C module implemented in these processor families does not support SM Bus or PM Bus

Regards,

Lavanya M R