Hello TI team,
It has been mentioned, shared memory will be used for core to core IPC.
Now, could you please confirm, Will this IPC consume external RAM or SOC provides some internal RAM for this IPC?
Regards,
Akshay
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Hello TI team,
It has been mentioned, shared memory will be used for core to core IPC.
Now, could you please confirm, Will this IPC consume external RAM or SOC provides some internal RAM for this IPC?
Regards,
Akshay
Hello Akshay,
Keep in mind that there are many different kinds of IPC. The examples we provide between Linux A53 and an MCU+ core are:
1) RPMsg (496 bytes of information passed at a time), which requires VIRTIO buffers to be defined in DDR memory, and
2) a shared memory example where each core directly reads and writes to a larger area of memory. This user-defined shared memory could be placed in DDR, or on-chip SRAM. You can find the zerocopy example here.
I'll link to some helpful AM62x Academy pages that might help you get started here:
How to run the out-of-the-box IPC example
Regards,
Nick