• State
  • Locked Locked
  • Replies 7 replies
  • Subscribers 98 subscribers
  • Views 491 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

L138 USB20 endpoint arbitration

Derek Robison
Prodigy 40 points

I am using the OMAP L138 USB 2.0 Mentor chip in peripheral mode.  I have configured enpoint 1 in and out for bulk.  I am using the CPPI dma engine to transfer large amounts of data to the IN endpoint.  During this time, I am using endpoint 2 IN for seperate communication.  I am not using CPPI to load endpoint 2.  If I load the endpoint 2 fifo with N bytes, and intiaiate a transfer, the data that is transfered on that endpoint is the first N bytes of my next endpoint 1 CPPI packet.  The next packet to transfer is the endpoint 1 packet including the data that was just sent out as endpoint 2 data.  This is very confusing.  My understanding is that the Mentor core should provide arbitration for the packets it is transmitting.  I do not understand why my endpoint 1 packet would be polluting my endpoint 2 packet.  My FIFO addresses are setup to point to different places in the memory space.  Please let me know if you have any ideas.  Thanks

Derek Robison

  • 0
    Expert 2110 points

    Hi,

    Just wonder if you are using the same TX submit queue for both EP 1 and EP 2 ? If yes, try to use separate queue for each of them.

    Second thing to check, make sure the channel is set correctly in the HPD.

    Third thing to check, is the next descriptor pointer. EP 1 1st packet only linked to EP 1 2nd packet, and so on.

    rgds,

    kc Wong

  • 0 in reply to Kiung Chung Wong
    Prodigy 40 points

    To the first item, to reitterate, I am only using CPPI DMA for endpoint 1, therefore I am not using a submit queue for endpoint 2.

    In the HPD the channel is set correctly.

    I am not currently linking the descriptors.  Next is null.

  • 0 in reply to Derek Robison
    Expert 2110 points

    That's interesting, seem like EP1 data overflows to EP2 FIFO.

    What is your FIFO configuration ? For example below is my FIFO configuration for high speed. Note that this is only for single packet buffering.

    Endpoint 1
            TX SZ = 512, ADDR = 64
            RX SZ = 512, ADDR = 576
    Endpoint 2
            TX SZ = 512, ADDR = 1088
            RX SZ = 512, ADDR = 1600
    Endpoint 3
            TX SZ = 512, ADDR = 2112
            RX SZ = 512, ADDR = 2624
    Endpoint 4
            TX SZ = 256, ADDR = 3136
            RX SZ = 256, ADDR = 3392

     

     

     

     

  • 0 in reply to Kiung Chung Wong
    Prodigy 40 points

    The interesting part that makes it seem like it is not an overflow is that it is the beginning of the next packet, not the end.  Anyhow, my fifo setup is:

    EP1 TX SZ = 512(6), ADDR = 64(8)
    EP1 RX SZ= 512(6), ADDR = 576(72)
    EP2 TX SZ = 512(6), ADDR = 1088(136)
    EP2 RX SZ = 512(6), ADDR = 1600(200)

    The numbers in parentheses are what goes into the register, as the size is 2^(m+3) and address is m/8.  So I have the same configuration as you.  Double packet buffering is disabled.

  • 0 in reply to Derek Robison
    Expert 2110 points

    If you disable EP1, and only send data (1 byte, 512 bytes) with EP2, do you always get the correct data at the host ?

  • 0 in reply to Kiung Chung Wong
    Prodigy 40 points

    Yes.  I even get the correct data with EP1 enabled, just not transmitting.  I have created a work around that protects my usb TX with a counting semaphore, so that EP2 will halt EP1 before transmit, and that works.  It seems that I should not need to do this though.

  • 0 in reply to Derek Robison
    Expert 2110 points

    Which DMA transfer mode that you are using, Transparent, RNDIS, Generic RNDIS or Linux CDC ?

    From your description, it seems to me when doing CPPI DMA for EP1, some packets end up in the EP2 FIFO.

    Not sure if you are using EP3. If not, may be you can try EP3. But, you still configure TX SZ = 512 and RX SZ = 512 for EP2. So that there is 1024 bytes between EP1 FIFO and EP3 FIFO. Then, you send data using EP3, see you still see EP1 packet or not in this case.