Other Parts Discussed in Thread: J784S4XEVM, DP83869HM
Our customer wants to use PCIe (M.2 NVMe), SGMII and USB3.0.
Is there a hardware design guide for SerDes on J784S4 devices?
Board Design and Layout Guidelines are only for LPDDR4.
Jacinto 7 LPDDR4 Board Design and Layout Guidelines (Rev. E)
The Schematic Checklist does not include guidelines for SerDes.
Jacinto7 AM6x/DRA8x/TDA4x Schematic Checklist (Rev. A)
J784S4XEVM and SK-AM69 alone do not support Ethernet with SGMII.
J721E EVM supports QSGMII Ethernet.
J721EXSOMXEVM
Common Processor Board Design Files (Rev. D)
\sprr411d\PROC080A_RP\PROC080A_SCH.pdf
For single SGMII PHY connection, QSGMII PHY connections can be referenced?
Best regards,
Daisuke
