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DRA829 and TDA4VM : Need RAT address for Jacinto DRA829J

Vinod Alase
Prodigy 20 points
Other Parts Discussed in Thread: DRA829J

Hello Team,

 

We are using the RAT with the CLS_Rat...() functions in a Jacinto DRA829J based project from the R5FSS1_CORE0 core.

 

For specific use cases, we need to read the RAT registers.
Unfortunately, in the J721E TRM (spruil1c.pdf) we did not find the Base Address of the RAT Instances for the R5FSS, like it is normaly the case for the other processor modules. We've also searched in the register documents.
They are some RAT references in the TRM chapter 2.4 "Processors View Map", but they are only 4 regions defined for the MAIN_R5FSS cores (and 3 regions for the MCU_R5FSS cores), not 16 regions like explained in the TRM chapter 8.4.
- Are these regions addresses in the chapter 2.4 the RAT base addresses? If yes, where are the 12 other ones?
- If not, where are defined the RAT base adresses?

 

Many thanks in advance for your help.


Regards,
Vinod Alase

  • 0
    TI__Guru** 111165 points

    Hi Vinod,

    The RAT is a private peripheral to each of the R5F cores, and can only be programmed/controlled by the software running on that R5F core. The address as such is the same on all R5Fs.

    There is no System bus address for the R5F RATs.

    regards

    Suman

  • 0 in reply to Suman Anna
    Prodigy 20 points

    Hi Suman,

     

    thanks you for your answer.

     

    We understand there is no global address for the RAT registers.

     

    Our question is: how to read the current configuration of the RAT for each core?

    - we did not find any function CSL_Rat...() to do that

    - therefore, we want to read the RAT registers like described in the registers documents of the TRM (J721E_registers3.pdf).

     

    In the J721E_registers3.pdf document, it is written: "Table 8-1 lists the memory-mapped registers for a RAT module...".

    Unfortunately, only the offset of each register is given, but no start address.

    There is also written "This section contains only the RAT register descriptions. For specific physical addresses associated with a RAT module, see the corresponding Registers section of the modules and subsystems listed in that have integrated RAT.".

     

    We've searched in the TRM spruil1c, and in chapter "6.3.3.9 R5FSS Memory View", we've found the following:

      - "RAT base address: This is determined by a bootstrap. This address is located within the VBUSP peripheral interface address space."

    But we did not find address values.

     

    What are the R5F local start address of the RAT memory-mapped registers?

    Thanks in advance

    Regards,

    Vinod Alase

  • 0 in reply to Vinod Alase
    TI__Guru** 111165 points

    Hi Vinod,

    Vinod Alase said:
    Unfortunately, only the offset of each register is given, but no start address.

    The address is mentioned in the R5FSS Memory Map table in the 2.4 Processors View Memory Map chapter of the TRM.

    The RAT Configuration space is where the RAT registers are present. The other ARMSS_RAT_REGIONx is merely specifying which are the Processor View memory ranges that can be used through RAT.

    Note that RAT usage is optional, and is primarily needed only for accessing > 32-bit system bus addresses on R5Fs.

    Vinod Alase said:
    - we did not find any function CSL_Rat...() to do that

    Which SDK are you using, and what firmwares are you using? What is the relevant core for your question? The latest SDKs do have some RAT usage within VisionApps firmwares.

    regards

    Suman

  • 0 in reply to Suman Anna
    Prodigy 20 points

    Hello Suman,

     

    Many thanks to point us to the base address, we did not understand firstly that this value was the register base address.

    Now we can read the translated addresses as expected.

    Thanks a lot!

     

    PS:

    We are using the pdk_jacinto_08_02_00_21. In the file csl_rat.h from ...packages\ti\csl\src\ip\rat\V0, there is a function to check if any of the 16 RAT regions is used ( “CSL_ratIsRegionTranslationEnabled()” ), but no function to get the concerned base and translated addresses. This is why we need to read directly the registers.

  • +1 in reply to Vinod Alase
    TI__Guru** 111165 points

    Hi Vinod,

    The packages/ti/csl/src/ip/rat/V0/csl_rat.h defines the CSL RAT API and associated structures, while the packages/ti/csl/src/ip/rat/V0/cslr_rat.h header file captures the register layout and definitions within each register.

    Both of them are generic IP layer definitions. There are many RAT instances in the SoC, and the base addresses for those are outside of the above header files.

    Following are couple of header files where the individual instance addresses are defined in the CSL folders.

    packages/ti/csl/soc/j721e/src/cslr_soc_baseaddress.h

    packages/ti/csl/soc/j721e/src/cslr_soc_c66_baseaddress.h

    packages/ti/csl/soc/j721e/src/cslr_soc_main_r5_baseaddress.h

    packages/ti/csl/soc/j721e/src/cslr_soc_mcu_r5_baseaddress.h

    regards

    Suman

  • 0
    Prodigy 20 points

    Hello Suman, 

    Thanks your valuable inputs on timely manner. It was great helpful. You can go ahead and close this thread. Thanks once again.

    Regards,

    Vinod