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EMIFA bus timing relation to EMA_CLK on OMAP-L138

Kent Salomonsen
Prodigy 10 points
Other Parts Discussed in Thread: OMAP-L138

Hi,

I am working on an FPGA design that communicates with an OMAP-L138 using the EMIFA *asynchronous* bus interface. 

It would be beneficial to my FPGA design if I could treat ema_clk as being *synchronous* to the EMIFA bus signals, and I suspect that it actually could be so - signal transitions seems to align to ema_clk and I have seen FPGA example design that actually assumes such a timing relationship!!

The question : Are the EMIFA bus signals in fact *synchronous* to ema_clk and if 'yes' is it possible to gain access to "TI approved" EMIFA pin timing relatively to ema_clk?

-Kent

 

 

  • 0
    TI__Genius 16956 points

    Kent,

    Yes, the EMA_CLK is an external version of the internal EMIF clock that is used to time the SETUP/STROBE/HOLD periods of an asynchronous access.  However, the delay timing relationship between EMA_CLK and the other asynchronous control signals has not been characterized.

    Regards,

    Brad