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AM6441: GPMC configuration in SYSCONFIG

Genius 17295 points
Part Number: AM6441
Other Parts Discussed in Thread: SYSCONFIG

Hello,

My customer has a question for GPMC configuration in SYSCONFIG(mcu_plus_sdk_am64x_09_00_00_35).
Now they are facing 2 problems.

1. Only 8bit can be selected for "Device Size". They want to use 16bit or 32bit.
2. Only one CS area can be configured. They want to use several CS areas.

I found the below similar post and I understand the above case 1 will be support in the future release.
How about case 2? 

https://e2e.ti.com/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers---internal/f/arm-based-microcontrollers---internal-forum/1286051/am2432-gpmc-configuration-in-sysconfig

And I understand that only 8bit cab be selected from SYSCONFIG. But is it possible to select 16bit or 32bit and configure multiple CS areas through driver API call?

Regards,
Satoshi Obata

  • Hello Satoshi Obata,

    I am looking at your queries, and you may expect a delayed reply .
    Regards,
    S.Anil
  • Hello Satoshi Obata,

    Can you please confirm which memory interface you are using—NAND memory or NOR memory?

    Regards,

    S.Anil.

  • Hello,

    It's NOR type memory.

    Regards,
    Oba

  • Hello Oba,

    In AM62X variants, there is a NAND interface card that is connected to AM62X SK kits. On the NAND interface cards, we currently support only 8-bit NAND devices, and the same AM62X code is integrated into AM64X devices.

    And I understand that only 8bit cab be selected from SYSCONFIG. But is it possible to select 16bit or 32bit and configure multiple CS areas through driver API call?

    Currently, we don't have API calls to change bit size and CS size.

    For bit selection and CS, you need to update this below generated code and make sure that for  other than 8-bit GPMC, you have to update pin settings for remaining pins as well since there is no support for selecting other than 8 bits in the system configuration.

    Currently, timing parameters are supported for NAND memories and not for NOR memories.

    Since the user needs to change the above changes, the timing parameters should also be updated for the NOR type.

    I need to confirm internally if there are any gpmc examples of NOR memory types in the future or not and let you know.

    Regards,

    S.Anil.