C6748 UPP Rx FIFO Overflow

I am sending data to the UPP port on a C6748 from an FPGA.  I am using clock, data and enable.  The data comes in bursts of 48, 16 bit words that I call system samples.  The burst rate is adjustable.  The UPP Clock is 40 MHz and is continuos (data is gated with enable).  The C6748 does some buffering and sends the data to an app running on a PC using Linux over Ethernet.  Each Ethernet packet is 1152 bytes (about 12 of my "system samples") and a sequence number.
For "data frame" of multiple system samples, the FPGA starts at 1 and counts up.  If the FPGA data reachs x"FFFF", the data resets to 1 and continues counting.
When I start cold and send three Ethernet Packets (24 "system samples", or a count of 1 to 1728), I expect the first Ethernet packet to contain the numbers 1 to 576, the second Ethernet Packet to contain the numbers 577 to 1152, and the third Ethernet packet to contain the number 1153 to 1728).  Instead, the first to Ethernet Packets are good.  The receivin app then stalls while it waits for the third packet.  When I send another three Ethernet packets, the orignal third packet is sent (verified by the sequence number).  However, there is gap in the date.  Instead of starting at 1153 as expected, it will start at some other number (say 1245), count up to 1728, start again at 1 and count to 92.  After this first set of ethernet packest is received and processed, there is no more stalling in the recieve app, but the data is offset by the same gap (i.e. it will start at 93, count to 1728, start at 1 and count to 92).
When I do this with tow Ethernet packets of data, the systems stalls in the second Ethernet packet until another set of data is sent.
What appears to be happenning is a buffer is not becoming available, the UPP FIFO is becoming full, and the FIFO data is being overwritten.  Is there a way to indicate the UPP FIFO is full and being overwritten without monitroing the wait line (it is not easily accessable)?