Part Number: AM3894
I have a customer who has a successful DDR design using AM3894 despite exceeding the clock and address maximum trace length specification by nearly 2x. The following is from the datasheet:
"
Given the clock and address pin locations on the processor and the DDR3 memories, the maximum possible Manhattan distance can be determined given the placement. Figure 9-37 and Figure 9-38 show this distance for four loads and two loads, respectively. It is from this distance that the specifications on the lengths of the transmission lines for the address bus are determined. CACLM is determined similarly for other address bus configurations; that is, it is based on the longest net of the CK and ADDR_CTRL net class. For CK and ADDR_CTRL routing, these specifications are contained in Table 9-24.
"
Table 9-24 lists A3 and A4 lengths (segments between DDR components) as 660mils maximum. This specification was missed during layout, and the constructed board has A3 and A4 lengths in the 1140 - 1210 mil range, which is very poor as a function of the Manhattan distance. Despite this, the DDR interface has been functioning without issue through days of run time. The text from the datasheet suggests that the max length specification is derived only from the Manhattan distance given the placement and not from any tangible timing or attenuation requirement.
I am trying to determine if we can be justified in leaving the design as is given its robustness in testing or if we are actually inviting a timing issue. (Note that all skew - or "matching" - requirements are met; this question only concerns max trace length.) Are the DDR clock and address maximum trace length specifications listed in Table 9-24 true requirements based on timing and signal quality or just suggestions based on the Manhattan distance of the components?
Thank you!
