This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Clock generators for TMS320C6678 chips

Other Parts Discussed in Thread: CDCE62005, CDCM61002, TMS320C6678

Hi All ,

In the hardware design guide it is recomended to use CDCE62005 clock generators for Shannon device. For symplicity we are planning to use CDCM61002 device in our hardware as this can be configured using hardware control pins. Does anyone forsee any issues if we go with thsi device for sourcing SYS_CLK and DDR3_CLK pins ?

-Anil

 

  • Hi Anil,

    As long as the CDCM61002 meets the jitter specification for the DDR3_CLK input then it should work fine.  Be sure to use the proper termination for the output driver selected and be sure that the clock isn't active until the CVDD voltage is present on the part.  It looks like you can use the CE pin for that purpose.

  • Hi Bill ,

    Thanks for the info. I have one more question regarding the clock generators. In the EVM for TMS320C66768 i observe that the clocks are synchronized i.e. the output of one CDCE62005 is fed as a reference to second CDCE62005(PRIREF pin) Is it mandatory that the clocks fed to TMS320C6678 processor (DDR_CLK,SYS_CLK,PASS_CLK,SRIO_SGMII_CLK etc)to be synchronized or can they be fed from seperate sources ?

    -Anil

     

  • Hi Anil,

    The clock sources to not need to be synchronized and can be fed from separate sources.