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AM6442: BCDMA CacheP_inv failed

Genius 13655 points

Part Number: AM6442

Hello Champs,

Customer wants to initialize 5 BCDMA out, each time he need to move data with DMA, he will automatically call the idle one, now the problem is in StructDMA.c, he calls BCDMA_MemoryCopy () to move the data and call Udma_ringDequeeRaw () in BCDMA_CheckCopyStatus () to see if the data is moved. After completion, the CacheP_inv() data is staged, but here if the program is staged, what if CacheP_inv() is not called here and the updated data is not visible at the destination address &data. 

Attached is the code.
struct_am64x-evm_r5fss0-0_nortos_ti-arm-clang.rar



Thanks
Regards
Shine

  • Hello Shine,

    Actually, cache_invalid is required after completion of DMA; otherwise, the processor can't read the data from destination memory.

    About cache_invalid is why it is needed. I have covered that topic in the below thread. Please check the last response for cache_invalid.

    https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1301437/tmds64evm-data-transfer-timing-for-bcdma-samples/4968961#4968961

    Regards,

    S.Anil.

  • Hello Shine,

    One more thing is that every time we don't need to call trpd_init for triggering dma,. trpd_init should be done only once.

    Next, to start dma, use the que_raw function, which is based on the user's requirements for where they need to start dma.

    Next, check the deque_raw function status as a completion of dma. After the completion of dma, do cache_inv. This step needs to be done based on how many times the user transfers DMA.

    Regards,

    S.Anil.

  • Hello S.Anil.

    Thank you very much for your great support.

    Customer understands why it needs to using CacheP_inv()after DMA transfer now,  the further question is that why the code runs out of control after executing CacheP_inv().


    Thanks
    Regards
    Shine

  • Hello Shina,

    I verified customer code yesterday at a high level .

    I need to check and debug further on my bench to see why the code goes out of control after calling cache_inv, and I will share the results once I have completed testing.

    Regards,

    S.Anil.

  • Hello Shina,

    I have looked at the code, and the customer is trying to do a DMA transfer with the 4 byte?

    Is this customer requirement to transfer only 4 bytes ? Can you please confirm how many bytes they need to transfer with the DMA ?

    Actually, I have verified from my side, and the code seems to be working, and there is no issue at caheP_Inv.

    and we don't need to call the App_udmaTrpdInit function every time, and this should be initiated only once since in the customer use case there is a change in

    the source and destination buffer.

    If you share above details I can give proper working code .

    Is it application on NO RTOS or free RTOS ?

    Regards,

    S.Anil.

  • Hello S.Anil.,

    Thank you very much.

    Customer wants to use DMA to transfer large number of data to offload CPU. The 4 bytes is only for debug purpose.  So can the number of transfer be configured as preferred? 

    He is using free RTOS. 

    Thankds
    Regards
    Shine

  • Shine,

    Yes, users can configure the large number of bytes transferred, and there is no problem.

    My suggestion is that if the customer wants to create 5 UDMA channels on RTOS side ,. they can take the below example and add it to more channels in syscfg. One suggestion is that the App_udmaTrpdInit API should be called only once and not every time.

    C:\ti\mcu_plus_sdk_am64x_09_00_00_31\examples\drivers\udma\udma_memcpy_interrupt\am64x-evm\r5fss0-0_freertos

    Let me know if they need or face any problem after creating the example .

    Regards,

    S.Anil.

  • Hello S.Anil.,

    Thank you very much.

    The code customer sent is modified based on  mcu_plus_sdk_am64x_09_00_00_31\examples\drivers\udma\udma_memcpy_interrupt\am64x-evm\r5fss0-0_freertos. Because he didn't want to use interrupt, he did a cache_inv after the status checking in main() function was complete,  but the program would fly after cache_inv. He wants to solve this problem of flying, 

    Thanks
    Regards
    Shine

  • Hello Shine,

    I don't have luck reproducing the issue on my side, and the example is working fine at my side.

    I am attaching the example; let me know if I missed anything.

    5707.udma_memcpy_interrupt_am64x-evm_r5fss0-0_freertos_ti-arm-clang.zip

    Regards,

    S.Anil.