Hello everyone,
I am undertaking interface of 04 nos C5510(McBSP) and MSP430(SPI ) with MSP430 as SPI master and the DSP as slave.
FSX receives CS/SS(active low) from MSP430 and other pins are connected as required
Configured McBSP for Clock stop mode
I have some queries regarding the McBSP configuration-
-Role of FREE, SOFT in SPCR2
-choice of FSRP
-choice of CLKXP/CLKRP/clksp-are they dont care
-choice of FSRM
-choice of GSYNC in SRGR2 (have chosen 1 for SRGR-McBSP synch)
- Do I have to enable DXENA bit of SPCR1 as McBSP2 of all 4 DSPs are sharing the same bus with the MSP430.
DXENA is enabled in case DX pins of multiple McBSPs are common, but I believe that is the case for McBSPs of the same DSP.