• State Resolved
  • Locked Locked
  • Replies 3 replies
  • Subscribers 98 subscribers
  • Views 339 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

PROCESSOR-SDK-AM62X: Reduce WKUP_CLKOUT0 output to 10 Mhz

Kumar Ashutosh
Intellectual 345 points
Part Number: PROCESSOR-SDK-AM62X


Hi Team,

We want to reduce the WKUP_CLKOUT0 clock output to 10 Mhz. We have checked in syscfg tool as shown below. Modifying the PLL2_HSDIV_B value is giving us the expected value of 10 Mhz. How I can adapt the same in code base and build the code to test the same. Kindly let me know the Process and also changing WKUP_CLKOUT0 to 10 MHz will impact other modules?

Also can we use devmem2 { address } [ type [ data ] ] to set the clock to 10 MHz for our initial Testing?

 

Regards,

Kumar Ashutosh

  • 0
    TI__Mastermind 28215 points

    you should be able to use devmem for testing.  There may be lock registers that need to be accounted for,  please check the TRM.

    Also check the other uses of the pll2_hsdiv that may be impacted by the change of frequency.

    —Paul 

  • 0 in reply to PaulM
    Intellectual 345 points

    Hi Paul,

    Thankyou for your response.

    I have tried changing the clock output value using devmem2 tool  but unable to generate the expected output. Below mentioned the commands executed.

    Syscfg tool register details:-

    As per TRM we need to write value "0x00000004" to select PLL2_HSDIV_B and frequency output was 50 Mhz. we need to configure separate register to change the divider value?

    Kindly let me know the steps by we need to execute to change the clock.

    Regards,

    Kumar Ashutosh

  • +1 in reply to Kumar Ashutosh
    TI__Mastermind 28215 points

    To change the frequency of  PLL2_HSDIV9 you will need to first unlock the registers as noted in the TRM:

     

    The PLL2 Lock registers are:

    pll2_LOCKKEY0     682010h
    pll2_LOCKKEY1     682014h

    You can then write to the require HSDIV value to the pll2_HSDIV_CTRL9 register at address 6820A4h

    Similar process for the CLKOUT_CTRL register.   

    First, unlock....

    For the clkout_ctrl register, you must unlock using the following registers:

    LOCK2_KICK0   10 9008h
    LOCK2_KICK1   10 900Ch

    Now you can write 4b100 to the CLKOUT_CTRL_WKUP_CLKOUT_SEL bit field of the  CLKOUT_CTRL register at 43008020h

    --Paul