TDA4VM: cpsw9g connected to PHY - TJA1101

Lukasz Bittner

Part Number: TDA4VM

Hi TI experts,

I'm trying to configure the CPSW9G Port 7 with PHY TJA1101 to set the ethernet communication on our custom board. I'm very beginner with this topic, so please let me know if my understanding is correct:

1) in linux kernel device tree I only need to add as was described under this link: https://git.ti.com/cgit/ti-linux-kernel/ti-linux-kernel/tree/Documentation/devicetree/bindings/net/ti,cpsw-virt-mac.txt?h=ti-linux-5.4.y

cpsw9g_virt_mac: main_r5fss_cpsw9g_virt_mac0 {
		compatible = "ti,j721e-cpsw-virt-mac";
		dma-coherent;
		ti,psil-base = <0x4a00>;
		ti,remote-name = "mpu_1_0_ethswitch-device-0";

		dmas = <&main_udmap 0xca00>,
		       <&main_udmap 0xca01>,
		       <&main_udmap 0xca02>,
		       <&main_udmap 0xca03>,
		       <&main_udmap 0xca04>,
		       <&main_udmap 0xca05>,
		       <&main_udmap 0xca06>,
		       <&main_udmap 0xca07>,
		       <&main_udmap 0x4a00>;
		dma-names = "tx0", "tx1", "tx2", "tx3",
			    "tx4", "tx5", "tx6", "tx7",
			    "rx";

		virt_emac_port {
			ti,label = "virt-port";
			/* local-mac-address = [0 0 0 0 0 0]; */
		};
	};

2) I do not need to add PHY and pins configuration in device tree - I need to configure these things in the linux driver 

Is my understanding correct?

over 2 years ago

0 Stanley Liu over 2 years ago

TI__Guru 50045 points

Hi,

Before digging into the implementation, have you evaluated the 2 networking options in SDK to decide which implementation to go with?

The 2 options are described at the following link.

https://software-dl.ti.com/jacinto7/esd/processor-sdk-linux-jacinto7/09_01_00_06/exports/docs/linux/Foundational_Components/Kernel/Kernel_Drivers/Network/CPSWng.html#cpswng

If network traffic only requires on A72 so no multi-core (A72 + R5s) network traffic is required, the Linux native driver can be used.

Otherwise, virtual mac driver on A72 + EthFW on R5 should be used.

The first question you asked is for virtual mac driver which means EthFW is running on R5.

With EthFW implementation, the PHY driver is on R5 so PHY control is done on R5 ENET PHY driver from PDK.

The pin mux can be done in bootloader or EthFW on R5. This is up to you.

However, I would suggest you to first evaluate your use case and pick the network implementation which suits for your use case.

0 Lukasz Bittner over 2 years ago in reply to Stanley Liu

Prodigy 80 points

Thanks for link, I'll check it. For now I only need run TI SDK on our custom board. So uboot and linux are running already but without ethernet communication. My design is the same like this

1) MCU CPSW2G RMII:

Main CPSW9G Port RMII

but for now I do not need configure MAC2MAC. My PHY is connected to pins named RMII1. I have configured these pins using PinMux tool

because AD18 is connected to the RMII ref clock

0 Lukasz Bittner over 2 years ago in reply to Lukasz Bittner

Prodigy 80 points

After read some part of native ethernet it seems I cannot use it because it doesn't support RMII mode and I use it.

0 Tanmay Patil over 2 years ago in reply to Lukasz Bittner

TI__Mastermind 43720 points

Hi Lukasz,

Sorry for the delay.

As you are using RMII, you need to specify this in the configuration. Where you need to specify this depends on what you are using as ethernet controller, Ethfw or Native Linux Driver. Can you please let me know this information.

The pinmux and schematic will be the same for both ethfw and Native linux driver.

For starters, to make changes in MCU_CPSW2G, you need to specify the correct phy-mode and phy-handle in the cpsw_port1 as follows.

&cpsw_port1 {
	phy-mode = "rmii";
	phy-handle = <&phy0>;
};

This is present in "arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts"

Regards,
Tanmay

0 Lukasz Bittner over 2 years ago in reply to Tanmay Patil

Prodigy 80 points

Hi Tanmy,

I'm trying to run virtual client because I read that

so I think I cannot use native ethernet switch because I use RMII and this is not listed that is supported. Am I right?

0 Tanmay Patil over 2 years ago in reply to Lukasz Bittner

TI__Mastermind 43720 points

Hi Lukasz,

Lukasz Bittner said:
so I think I cannot use native ethernet switch because I use RMII and this is not listed that is supported. Am I right?

This is not true. This list mentions what is verified as the part of SDK release and that we call out as supported. As we do not have a RMII phy on the EVM, We do not verify RMII with every release. But both the ethfw and native linux driver support RMII.

You should first decide if you want to use Ethfw or Native Linux driver based on your system design and then we can work on enabling the RMII link with your selected controller.

Regards,
Tanmay

0 Lukasz Bittner over 2 years ago in reply to Tanmay Patil

Prodigy 80 points

I would like to try to enable native linux driver. I understand I have to prepare similar file to this (according to my hardware):

/cfs-file/__key/communityserver-discussions-components-files/791/k3_2D00_j721e_2D00_gesi_2D00_exp_2D00_board.dts

I took this link from this thread: https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1166334/faq-tda4vm-how-to-move-to-native-linux-driver-on-sdk-8-4-for-j7-and-dra8-devices?tisearch=e2e-sitesearch&keymatch=faq%3Atrue

I wonder only what I should place here

cpsw9g_phy15: ethernet-phy@15 {
 reg = <15>;
 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
 ti,min-output-impedance;
 };

Can you give some hints what should be here for TJA1101?

0 Tanmay Patil over 2 years ago in reply to Lukasz Bittner

TI__Mastermind 43720 points

Hi Lukasz,

The" reg" property here is mandatory. It tells the driver the address of the phy on the MDIO lines. This value would be bootstrapped into your schematic design.

Apart from this, other thing are phy specific properties. You can reach out to phy manufacturer (NXP in your case) for details on this.

Regards,
Tanmay

0 Lukasz Bittner over 2 years ago in reply to Tanmay Patil

Prodigy 80 points

Hi,

I have provided my changes, and of course it isn't working.

this is my configuration of pins:

mdio_pins_default: mdio-pins-default {
 pinctrl-single,pins = <
 J721E_IOPAD(0x1bc, PIN_OUTPUT, 0) /* (V24) MDIO0_MDC */
 J721E_IOPAD(0x1b8, PIN_INPUT, 0) /* (V26) MDIO0_MDIO */
 >;
 };

rmii1_pins_default: rmii1_pins_default {
 pinctrl-single,pins = <
 J721E_IOPAD(0x158, PIN_INPUT, 1) /* (U23) RGMII5_TX_CTL.RMII7_CRS_DV */
 J721E_IOPAD(0x184, PIN_INPUT, 1) /* (T23) RGMII5_RD0.RMII7_RXD0 */
 J721E_IOPAD(0x180, PIN_INPUT, 1) /* (R23) RGMII5_RD1.RMII7_RXD1 */
 J721E_IOPAD(0x15c, PIN_INPUT, 1) /* (U26) RGMII5_RX_CTL.RMII7_RX_ER */
 J721E_IOPAD(0x16c, PIN_OUTPUT, 1) /* (U28) RGMII5_TD0.RMII7_TXD0 */
 J721E_IOPAD(0x168, PIN_OUTPUT, 1) /* (V27) RGMII5_TD1.RMII7_TXD1 */
 J721E_IOPAD(0x170, PIN_OUTPUT, 1) /* (U29) RGMII5_TXC.RMII7_TX_EN */
 >;
 };

 rmii_pins_default: rmii_pins_default {
 pinctrl-single,pins = <
 J721E_IOPAD(0xac, PIN_INPUT_PULLDOWN, 5) /* (AD18) PRG1_MDIO0_MDC.RMII_REF_CLK */
 >;
 };

 phy_en_pins_default: phy_en_pins_default {
 pinctrl-single,pins = <
 J721E_IOPAD(0xe0, PIN_OUTPUT_PULLUP, 0) /* (AH27) - enbale pin of PHY*/
 >;
 };

 phy_rst_pins_default: phy_rst_pins_default {
 pinctrl-single,pins = <
 J721E_IOPAD(0xdc, PIN_OUTPUT_PULLUP, 0) /* (AJ28) - reset pin of PHY */
 >;
 };

I have doubts related to AD18 - based on PHY configuration the ref clock should be input for TJA1101, so I think AD18 should be output, but TIPinMux doesn't allow me for this, I cannot disable RX:

and on schematic this looks like an output

this is the rest of configuration:

&cpsw0 {
 status = "okay";
 pinctrl-names = "default";
 pinctrl-0 = <&mdio_pins_default
 &rmii1_pins_default
 &rmii_pins_default
 &phy_en_pins_default
 &phy_rst_pins_default>;
};

&davinci_mdio {
 #address-cells = <1>;
 #size-cells = <0>;
 bus_freq = <1000000>;
 phy0: ethernet-phy@0 {
 compatible = "ethernet-phy-ieee802.3-c22";
 reg = <0>;
 tja110x,refclk_in;
 };
};

&cpsw0_port1 {
 phy-mode = "rmii";
 phy-handle = <&phy0>;
};

TJA1101 has address 0x00 on a bus. I omitted interrupt pin for now. I'm trying to communicate with the PHY by bus at first step.

I haven't added this part - reset pin :

cpsw9g_mdio {
 bus_freq = <1000000>;
 reset-gpios = <&exp2 17 GPIO_ACTIVE_LOW>;
 reset-post-delay-us = <120000>;

--------

&exp2 {
 qsgmii-line-hog {
 gpio-hog;
 gpios = <16 GPIO_ACTIVE_HIGH>;
 output-low;
 line-name = "qsgmii-pwrdn-line";
 };
};

The reason is I do not know which values for port and pins set for PRG0_PRU0_GPO11 that is my reset pin for PHY.

0 Tanmay Patil over 2 years ago in reply to Lukasz Bittner

TI__Mastermind 43720 points

Hi,

Give me some time to go through the information you provided.

I will respond early next week.

Regards,

Tanmay

0 Lukasz Bittner over 2 years ago in reply to Tanmay Patil

Prodigy 80 points

Hi, thanks, I'm waiting for your response. Yesterday I have provided some changes in code because I figure out some mistakes.

rmii1_pins_default: rmii1_pins_default {
 pinctrl-single,pins = <
 J721E_IOPAD(0x158, PIN_INPUT, 1) /* (U23) RGMII5_TX_CTL.RMII7_CRS_DV */
 J721E_IOPAD(0x184, PIN_INPUT, 1) /* (T23) RGMII5_RD0.RMII7_RXD0 */
 J721E_IOPAD(0x180, PIN_INPUT, 1) /* (R23) RGMII5_RD1.RMII7_RXD1 */
 J721E_IOPAD(0x15c, PIN_INPUT, 1) /* (U26) RGMII5_RX_CTL.RMII7_RX_ER */
 J721E_IOPAD(0x16c, PIN_OUTPUT, 1) /* (U28) RGMII5_TD0.RMII7_TXD0 */
 J721E_IOPAD(0x168, PIN_OUTPUT, 1) /* (V27) RGMII5_TD1.RMII7_TXD1 */
 J721E_IOPAD(0x170, PIN_OUTPUT, 1) /* (U29) RGMII5_TXC.RMII7_TX_EN */
 >;
 };

 rmii_pins_default: rmii_pins_default {
 pinctrl-single,pins = <
 J721E_IOPAD(0xac, PIN_INPUT_PULLDOWN, 5) /* (AD18) PRG1_MDIO0_MDC.RMII_REF_CLK */
 >;
 };

 phy_en_pins_default: phy_en_pins_default {
 pinctrl-single,pins = <
 J721E_IOPAD(0xe0, PIN_OUTPUT_PULLUP, 7) /* (AH27) - enbale pin of PHY*/
 >;
 };

 phy_rst_pins_default: phy_rst_pins_default {
 pinctrl-single,pins = <
 J721E_IOPAD(0xdc, PIN_OUTPUT, 7) /* (AJ28) - reset pin of PHY */
 >;
 };

 mdio_pins_default: mdio-pins-default {
 pinctrl-single,pins = <
 J721E_IOPAD(0x1bc, PIN_OUTPUT, 0) /* (V24) MDIO0_MDC */
 J721E_IOPAD(0x1b8, PIN_INPUT, 0) /* (V26) MDIO0_MDIO */
 >;
 };

For RST and EN pin the mode was wrong - it should be set to 7 - according to the PinMuxTool.

And next looks like this:

&{/} {
 enable_pin_phy {
 pinctrl-names = "default";
 pinctrl-0 = <&phy_en_pins_default>;
 gpios = <&main_gpio0 55 GPIO_ACTIVE_HIGH>;
 default-state = "on";
 };
};

&cpsw0 {
 status = "okay";
 pinctrl-names = "default";
 pinctrl-0 = <&mdio_pins_default
 &rmii1_pins_default
 &rmii_pins_default>;
};

&cpsw0_port1 {
 phy-handle = <&cpsw9g_phy0>;
 phy-mode = "rmii";
 mac-address = [AA BB CC DD EE FF];
};

&cpsw9g_mdio {
 bus_freq = <1000000>;
 pinctrl-names = "default";
 pinctrl-0 = <&phy_rst_pins_default>;
 reset-gpios = <&main_gpio0 54 GPIO_ACTIVE_LOW>; /* (AJ28) - reset pin of PHY */
 reset-post-delay-us = <120000>;
 #address-cells = <1>;
 #size-cells = <0>;

 cpsw9g_phy0: ethernet-phy@0 {
 compatible = "ethernet-phy-ieee802.3-c22";
 reg = <0>;
 tja110x,refclk_in;
 };
};

and of course it doesn't work as well.For now I get information: "mdio couldn't get reset gpio"

0 Tanmay Patil over 2 years ago in reply to Lukasz Bittner

TI__Mastermind 43720 points

Hi Lukasz,

I see that this message is for cosw9g.

Is your CPSW2G working and you are only having issues with CPSW9G?

Regards,

Tanmay

0 Lukasz Bittner over 2 years ago in reply to Tanmay Patil

Prodigy 80 points

Hi,

No. My understanding is, CPSW2G I can only mapped to MCU_RGMII, and in my case it is connected to RGMII6 pins using MAC2MAC. So I decided to not configure it. PHY is connected to RGMII5 pins and I think only these pins and CPSW9G I have to set up.

0 Tanmay Patil over 2 years ago in reply to Lukasz Bittner

TI__Mastermind 43720 points

Hi Lukasz

Lukasz Bittner said:
For now I get information: "mdio couldn't get reset gpio"

This means that The phy itself is not coming out of reset for you. You tried things earlier with a gpio-hog. Was the phy powered-up using that?

Lukasz Bittner said:
I have provided my changes, and of course it isn't working.

According to the logs you shared earlier, the the CPSW9G driver instance does not recognise the phy. Your MDIO pins are correct, hence the phy must not be out of reset. Can this be confirmed?

Regards,
Tanmay

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TDA4VM: cpsw9g connected to PHY - TJA1101