TDA4VM-Q1: EMMC CLK frequency

Zehui Li

Intellectual 540 points

Part Number: TDA4VM-Q1

Hi,

Why the max frequency of High Speed SDR/DDR is 50Mhz? While the JESD84-B51 has the max frequency 52Mhz.

over 2 years ago

+1 Diwakar Dhyani over 2 years ago

TI__Guru 69315 points

Hi Zehui

These are the divisor value which can set in the mmc host controller register ,So if you want to set to 52Mhz the closest you can go is 50Mhz which is 200MHz/4 (input freq /Divisior)

That is why the Max frequency is given as 50Mhz.

Regards
Diwakar

0 Zehui Li over 2 years ago in reply to Diwakar Dhyani

Intellectual 540 points

Hi Diwakar,

1.Is it a common implementation for TI processors? I check AM62. It's also max 50Mhz.

2.I think this only makes the data rate a little slower. No other influence, right? Please check it.

3.Is there other slight changes from JESD84-B51 for EMMC use?

0 Diwakar Dhyani over 2 years ago in reply to Zehui Li

TI__Guru 69315 points

HI Zehui

Zehui Li said:
1.Is it a common implementation for TI processors? I check AM62. It's also max 50Mhz.

That is because of the same IP.

Zehui Li said:
3.Is there other slight changes from JESD84-B51 for EMMC use?

No other changes.

Regards
Diwakar

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TDA4VM-Q1: EMMC CLK frequency