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PROCESSOR-SDK-J784S4: [SA5] Multi mastering of Graph and Nodes

Sivaguru Subramanian
Prodigy 250 points

Part Number: PROCESSOR-SDK-J784S4
Other Parts Discussed in Thread: TDA4VM

Currently the open VX nodes and Graphs are created in the A72 core.

For our project purpose we would need to create the Graphs and Nodes in the Main R5F core as well.

Need to create the graphs and node in both A72 and R5F and that has to be controlled by each master (A72 nodes/ graphs by A72 and R5F node/  graphs by R5F). Is it possible to control the nodes in multiple masters.

Kindly share us the sample applications for the same if available.

  • 0
    TI__Guru* 90681 points

    Hi,

    The SDK currently does not support multiple host for OpenVX. Currently there is no plan to support this feature.

    The SDK supports only A72 as OpenVX host.

    Additionally, you could follow the below FAQ for making R5 as host. 

    (+) [FAQ] TDA4VM: OpenVX Host on R5F and node Target on A72 (Linux) - Processors forum - Processors - TI E2E support forums

    But currently at a time there will be only one OpenVX host supported

    Regards,

    Nikhil

  • 0 in reply to Nikhil Dasan
    Prodigy 250 points

    Hi Nikhil,

    Thanks for the update.

    Have few questions as follows,

    1. When there is a failure observed in the R5F nodes how the recovery will take place? Will the node start from the first step if the graph is informed with the failure or it will continue from the failure step?

    2. Do we have a mechanism to report the failure at the openVx graph at the node level?

  • 0 in reply to Sivaguru Subramanian
    TI__Guru* 90681 points

    Hi,

    Each node implementation is different. So failure in the logics inside the node could be notified to user using VX_LOGS

    If there is an error in the framework during execution of the node, i.e. for eg. if there is any error calling the create_callback of the node, then on the A72 side, the vxVerifyGraph() would fail and graph would not execute.

    During runtime, if the MCU2_0 core crashes, then the IPC communication from A72 to trigger the process node would be on wait state and hangs the graph.

    Regards,

    Nikhil

  • 0 in reply to Nikhil Dasan
    Prodigy 250 points

    Thanks Nikhil.

    Kindly provide information on the below,

    1. Check with TI if TI OVX master can be QM and slave on R5F can be ASIL.

      - In our case A72 is QM, R5F is ASIL.

      - If A72 is mastering the graph is there any chance to verify the graph in R5F?


    2. Check what additional verification is done on the data between A72 and R5F

        - How the data shall be verified?


    3. FFI: data, peripheral - ISP driver not shared, Real time - time stamp checks

     

  • 0 in reply to Sivaguru Subramanian
    TI__Guru* 90681 points

    Hi,

    Sivaguru Subramanian said:
    - If A72 is mastering the graph is there any chance to verify the graph in R5F?

    Verification must always be done by the Host itself as this involves allocation of memory for the OpenVX data objects and other resources.

    Nikhil Dasan said:
    (+) [FAQ] TDA4VM: OpenVX Host on R5F and node Target on A72 (Linux) - Processors forum - Processors - TI E2E support forums

    As mentioned earlier, the SDK supports only A72 as master (HOST) and other cores as slave. 

    The FAQ with R5 as host is just a proof of concept from TI's end.

    Sivaguru Subramanian said:
    - How the data shall be verified?

    All the verification and validation happens in the vxVerifyGraph(). This internally calls the validation callback function of each node on the host side, where user could add additional verification if needed. This will be on the Host side

    On the R5 side, user could add additional verification in the create callback of the node, which is also called during the vxVerifyGraph().

    Regards,

    Nikhil