AM6422: PRU issues

Ethan Tian

Part Number: AM6422

Hi experts

Ask a question about PRU.
ICSSG_PRU_CYCLE Register is described in the development documentation. (Offset = Ch) [reset = 0h]
1,What does the recorded data in CYCLECNT represent? Does the CYCLECNT register accumulate to 200000000 in 1s with the pru frequency set to 200M?
2,How to read CYCLECNT using assembly?
3,what is the actual time it takes to read this reg?

There is also an IEP_COUNT in the PRU constant table
1,how to read the count values in PRU_IEP Registers?
2,What is the count value in PRU_IEP Register mean? Is it an RTU cycle?
3,what is the actual time it takes to read this reg?

over 2 years ago

0 Achala Ram over 2 years ago

TI__Expert 4000 points

Hi Ethan,

1. What does the recorded data in CYCLECNT represent? Does the CYCLECNT register accumulate to 200000000 in 1s with the pru frequency set to 200M?

Ans. Yes, This register counts the number of PRU cycles and for each PRU cycle this count value is increased by 1.

2. How to read CYCLECNT using assembly?

Ans. By using LBCO instruction:

LBCO &R0, c11, 0xC, 4

This instruction stores the PRU cycle count value from the cycle count register to the R0 register.

Follow the link PRU Assembly Instruction User Guide for assembly instructions.

and see section 6.4.14.1 in AM64x TRM for CTRL register base address & offsets. AM64x/AM243x Technical Reference Manual (Rev. H) (ti.com)

Also see constant table section 6.4.5.2.1 in TRM for base address mapping.

3. what is the actual time it takes to read this reg?

Ans. It depends on the length and other factors. see this post for time calculation [FAQ] PRU: How do I calculate read and write latencies? - Processors forum - Processors - TI E2E support forums

////////////--------------------------------------------/////////////////

Please see section 6.4.14.9 in TAM64x TRM for IEP registers. AM64x/AM243x Technical Reference Manual (Rev. H) (ti.com)

1. how to read the count values in PRU_IEP Registers?

Ans. Same as cycle count just you need to change base address & offset.

LBCO &R0, c26, 0x10, 8

This instruction stores the IEP count value from the IEP count registers into the R0 and R1 registers.

There are two count registers for the IEP clock so R0 will store the first 4 byte values from the count value low register and R1 will store

the next 4 byte values from the count value high register.

2. What is the count value in PRU_IEP Register mean? Is it an RTU cycle?

Ans. No, it is not RTU cycle. These are the count registers for the IEP clock and these counts are incremented on each positive edge of the IEP clock. First the low count register reaches its maximum values, then later the high register starts increasing.

3. what is the actual time it takes to read this reg?

Ans. Please see this page [FAQ] PRU: How do I calculate read and write latencies? - Processors forum - Processors - TI E2E support forums

Thanks & Regards,

Achala Ram

0 Ethan Tian over 2 years ago in reply to Achala Ram

TI__Intellectual 1872 points

Thanks Achala

From the introduction of ICSSG_PRU_CYCLE Register, we can know that it has read and write attributes, and reset value is 0.
However, in actual use, I found that the write operation would clear the cnt value to zero.
For example:
LDI TIME_NOW.w0, 1000010001111110b
LDI TIME_NOW.w2, 11110b
SBCO &TIME_NOW, c11, 0xc, 4
QBBS record_every_start, r31, 19
LBCO &TIME_NOW, c11, 0xc, 4
SBCO &TIME_NOW, c24, ADDR_REP, 4
Halt
At this time, the value read from the ADDR_REP address will be 3. instead of the expected value 111101000010001111110b+3.

Please help me understand this issue

+1 Achala Ram over 2 years ago in reply to Ethan Tian

TI__Expert 4000 points

Hi Ethan,

This is expected, any write operation on the ICSSG_PRU_CYCLE register resets the cnt value to zero. The ICSSG_PRU_CYCLE register has the write attribute only to clear the cycle cnt value, not to write any value.