Part Number: TDA4AL-Q1
Hi, TI Expert,
Our customer try to implement RGMII MAC to MAC communication, we do two experiments.
TEST 1. TDA4 & MCU TC397 connect to each other by ethernet switch (88Q5152)
Base on this block diagram, we already check TDA4 & TC397 ethernet connection success when ethernet switch as bridge.
Base on TEST1,signal chart as below,
Yellow (TDA4_TXC) -> TXC CLOCK, TDA4 transmit to 88Q5152 , 50MHZ
Blue (TDA4_RXC) -> RXC CLOCK, TDA4 receiver from 88Q5152, 125MHZ
Red (TC397_RXC) -> RXC CLOCK, TC397 receive clock from 88Q5152, 125MHZ
Green (TC397_TXC) -> TXC CLOCK, TC397 transmit clock to 88Q5152, 125MHZ
TEST 2. TDA4 & TC397 direct connect to each without ethernet switch (88Q5152)
I think we do not do any software modify for both side, and we found connection failed.
MAC to MAC should be like this
My Question :
Q1 : Base on "TEST 1", Why TDA4 TXC clock is 50MHz?
Base on 1Gbps "fixed-link" rate setting, TXC clock should be 125MHZ, But it is very strange, Why ethernet communication is still working?
Q2 : Base on "TEST 1", How to let TDA4 TXC clock works on 125MHZ?
Q3 : Base on "TEST 2", we try to dump "CPSW_CPSW_NU_CPSW_NU_CPSW_NU_STAT_x" register, Why do we not get any frame on port1?
eth1 means main domain RGMII1 for TDA4
if connection success(TEST 1), it should be like as below.
root@j721s2-evm:~# ./cpsw_all_reg_print
===============================
Menu
===============================
0: Clear Stats : CPSW 2G
1: Print Stats : CPSW 2G
2: Print ALE : CPSW 2G
3: Print Enet CFG : CPSW 2G
4: Verify Enet Ctrl CFG : CPSW 2G
5: Print MAC Config : CPSW 2G
6: Clear Stats : CPSW MAIN 2G
7: Print Stats : CPSW MAIN 2G
8: Print ALE : CPSW MAIN 2G
9: Print Enet CFG : CPSW MAIN 2G
10: Verify Enet Ctrl CFG : CPSW MAIN 2G
11: Print MAC Config : CPSW MAIN 2G
Make your choice : 7
STATS
--------------------------------
PORT0 STATS
--------------------------------
STAT_0_RXGOODFRAMES = 2e
STAT_0_RXBROADCASTFRAMES = f
STAT_0_RXMULTICASTFRAMES = 1f
STAT_0_RXOCTETS = 1d16
STAT_0_TXGOODFRAMES = d
STAT_0_TXBROADCASTFRAMES = 9
STAT_0_TXMULTICASTFRAMES = 4
STAT_0_TXOCTETS = 90c
STAT_0_OCTETFRAMES64 = 7
STAT_0_OCTETFRAMES65T127 = 19
STAT_0_OCTETFRAMES128T255 = f
STAT_0_OCTETFRAMES256T511 = c
STAT_0_NETOCTETS = 2622
--------------------------------
PORT1 STATS
--------------------------------
STAT_1_RXGOODFRAMES = 15
STAT_1_RXBROADCASTFRAMES = 9
STAT_1_RXMULTICASTFRAMES = c
STAT_1_ALE_DROP = 8
STAT_1_RXOCTETS = ffc
STAT_1_TXGOODFRAMES = 2e
STAT_1_TXBROADCASTFRAMES = f
STAT_1_TXMULTICASTFRAMES = 1f
STAT_1_TXOCTETS = 1d16
STAT_1_OCTETFRAMES64 = 7
STAT_1_OCTETFRAMES65T127 = 19
STAT_1_OCTETFRAMES128T255 = 17
STAT_1_OCTETFRAMES256T511 = c
STAT_1_NETOCTETS = 2d12
STAT_1_PORTMASK_DROP = 8
STAT_1_ALE_UNKN_MLT = c
STAT_1_ALE_UNKN_MLT_BCNT = 87c
STAT_1_ALE_UNKN_BRD = 9
STAT_1_ALE_UNKN_BRD_BCNT = 780
STAT_1_TX_PRI_REG [0]= 2e
STAT_1_TX_PRI_BCNT_REG [0]= 1d16
if connection failed (TEST 2), it should be like as below.
STAT_0_RXGOODFRAMES = 2b
STAT_0_RXBROADCASTFRAMES = a
STAT_0_RXMULTICASTFRAMES = 21
STAT_0_RXOCTETS = 1cea
STAT_0_OCTETFRAMES64 = 2
STAT_0_OCTETFRAMES65T127 = 16
STAT_0_OCTETFRAMES128T255 = 6
STAT_0_OCTETFRAMES256T511 = d
STAT_0_NETOCTETS = 1cea
--------------------------------
PORT1 STATS
--------------------------------
STAT_1_TXGOODFRAMES = 2b
STAT_1_TXBROADCASTFRAMES = a
STAT_1_TXMULTICASTFRAMES = 21
STAT_1_TXOCTETS = 1cea
STAT_1_OCTETFRAMES64 = 2
STAT_1_OCTETFRAMES65T127 = 16
STAT_1_OCTETFRAMES128T255 = 6
STAT_1_OCTETFRAMES256T511 = d
STAT_1_NETOCTETS = 1cea
STAT_1_TX_PRI_REG [0]= 2b
STAT_1_TX_PRI_BCNT_REG [0]= 1cea
I think we need any suggestion to debug this issue.
for example, register or software ...
Many Thanks
Gibbs
