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TDA4VM: RGMII internal delay

Sergio Annoni
Prodigy 80 points
Part Number: TDA4VM

Hi TI experts. I'm currently working on a proprietary designed hardware based on TDA4VM Soc (PG. 1.1). My hardware is exporting one ethernet interface connected to the ENET Port 8 of CPSW0 peripheral. The port is configured as RGMII and it is connected to a DP83867 PHY. The CPSW0 and the PHY are properly configured and the ethernet interface is working fine. I have a doubt however about the configuration of the Internal transmit delay on TDA4. In the datasheet, paragraph 12.2.2.1.2 CPSW0 Not Supported Features it is reported the following sentence:

- RGMII Internal Delay Mode disabled

According to the datasheet it seems that "RGMII Internal Delay Mode disabled" it is not supported on the CPSW0 peripheral.

Nevertheless I found the bit RGMII_ID_MODE of the CTRLMMR_ENET8_CTRL register configured to 1 and an oscilloscope measurements shows there is no internal delay on the RGMII bus. I noticed the RGMII_ID_MODE is explicitly set to 1 in the TI SDK code (cfr. board/src/j721e_evm/board_ethernet_config.c, function Board_cpsw9gEthConfig). This is confusing me because that seems the SDK is expressly disabling the internal delay in case of RGMII mode is selected. But according to the documentation this capability seems not supported nor recommended.

What is actually the correct configuration expected by TI for the  CTRLMMR_ENET8_CTRL  and the RGMII_ID_MODE  mode? Is it correct to keep the Internal delay disabled (as implemented by SDK) or do I have to kee4p it enabled and set that bit to 0?

  • 0
    TI__Genius 9295 points

    Hi Sergio,

    RGMII delay can be enabled either on the TDA4 side or PHY side, but not on both.

    I'm not sure about the comment on datasheet, but our default configuration in SDK is TDA4 internal delay is disabled (RGMII_ID_MODE=1). And the RGMII delay is programmed on the DP83867 PHY side through the following registers:

    • Reg addr 0x32 - RGMII Control Register (RGMIICTL)
    • Reg addr 0x86 - RGMII Delay Control Register (RGMIIDCTL)
  • 0 in reply to Misael Lopez Cruz
    Prodigy 80 points

    Thanks Misael, actually I have the following settings:

    RGMIICTL = 0x00d3

    RGMIIDCTL = 0x00b7

    CTRLMMR_ENET8_CTRL = 0x000A

    This means internal delay on TDA4 is disabled while 3.00 ns delay on Tx and 2.00 ns delay on Rx are configured on the PHY. 

    I'm not sure about the meaning of RGMIICTL register bits RGMII_TX_CLK_DELAY and RGMII_RX_CLK_DELAY and how they are correlated (if they are) to the delays configured on the PHY? Are the delays configured on the PHY totally independent from RGMII Clock Delay shift configuration?

  • 0 in reply to Sergio Annoni
    TI__Guru 63850 points

    Hi,

    Sergio Annoni said:
    This means internal delay on TDA4 is disabled while 3.00 ns delay on Tx and 2.00 ns delay on Rx are configured on the PHY. 

    Yes.

    Sergio Annoni said:
    I'm not sure about the meaning of RGMIICTL register bits RGMII_TX_CLK_DELAY and RGMII_RX_CLK_DELAY and how they are correlated (if they are) to the delays configured on the PHY?

    RGMIICTL register determines whether clock skew to applied to not.
    If RGMIICTL register bits RGMII_TX_CLK_DELAY and RGMII_RX_CLK_DELAY are set to 0's means, no clock skew applied for RGMII Tx & Rx clock.
    The skew value will be configured from RGMIIDCTL register, Please refer to below from PHY Data sheet.

    Sergio Annoni said:
    Are the delays configured on the PHY totally independent from RGMII Clock Delay shift configuration?

    Do you mean RGMII delay requirement? If so, the delay configured at PHY is related to RGMII delay requirement.

    Usually one can fulfill the RGMII delay requirement using any of below options.
    1. Configure both Tx & Rx delay at MAC side, if MAC is supported.
    2. Configure both Tx & Rx delay at PHY side, If PHY is supported.
    3. Enable delay from PCB traces while design of Board, In this case no need to enable delay at PHY or MAC.
    4. Configure the Tx delay at MAC side, and Rx delay at PHY side.

    Best Regards,
    Sudheer