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TMDXEVM6678L Smart Reflex Circuit

Courtney Cooley
Prodigy 235 points
Other Parts Discussed in Thread: UCD9222

I have a couple of questions regarding the Smart Reflex power circuit used on the TMDXEVM6678L eval board…

 

1.      The four VID2 pins of the UCD9222 device are connected to the FPGA. I believe these pins are used to control the dynamic voltage on the associate rail. Since the voltage on Rail#2 is fixed, rather than dynamic, what is the FPGA doing with these pins?

          a.  Do these pins need to be connected if there is no need for a dynamic voltage on Rail#2 of the UCD9222 device?

b.    If they do not need to be connected, how should they be terminated?

2.      The PMBus of the UCD9222 device is connected to the FPGA, as well as to a test header. Does the bus need to be connected to another device for some reason, or is a header sufficient?

3.      According to the EN1/EN2 description in the UCD9222 datasheet, “When the ON_OFF_CONFIG setting is configured to respond the PMBus_Cntrl pin, the PMBus_Cntrl pin signal will be logically ANDed withthe rail’s EN pin signal.” I assume that all ON_OFF_CONFIG options (not just the PMBust_Cntrl pin option) will be logically ANDed with the rail's EN pin signal, so that no matter what setting is selected the EN signal must be asserted in order for the rail to turn on. For example, if the ON_OFF_CONFIG command were such that the rails were set to turn on automatically, they would not turn on until the enable signals were asserted. Can you please confirm this?

 

Thank you very much for you help.

-Courtney

  • 0
    TI__Mastermind 42545 points

    1a.  Do these pins need to be connected if there is no need for a dynamic voltage on Rail#2 of the UCD9222 device?
    No, they do not need to be connected. 

    1b.  If they do not need to be connected, how should they be terminated?
    They are terminated internally and can be left floating.

    2. The PMBus of the UCD9222 device is connected to the FPGA, as well as to a test header. Does the bus need to be connected to another device for some reason, or is a header sufficient?
    If you are using the Fusion tool to program the UCD9222 only the header is needed.  The connection to the FPGA is for internal development purposes only.  Note that only the PMBUS_CLK, PMBUS_DAT and ground are needed for communications with the Fusion software.  The PMBUS_CNTL signal is used by the FPGA to enable the power supply during the sequencing.

    3. According to the EN1/EN2 description in the UCD9222 datasheet, "When the ON_OFF_CONFIG setting is configured to respond the PMBus_Cntrl pin, the PMBus_Cntrl pin signal will be logically ANDed with the rail’s EN pin signal."  I assume that all ON_OFF_CONFIG options (not just the PMBust_Cntrl pin option) will be logically ANDed with the rail's EN pin signal, so that no matter what setting is selected the EN signal must be asserted in order for the rail to turn on. For example, if the ON_OFF_CONFIG command were such that the rails were set to turn on automatically, they would not turn on until the enable signals were asserted. Can you please confirm this?
    If the ON_OFF_CONFIG is set to use the control pin then the PMBUS_CNTL and the ENx pin must be high to enable the power supply controller.  If it is set for always converting it will ignore the state of the PMBUS_CNTL and ENx pins and enable the supply as soon as power is applied.   

    The UCD9222 has the capibility of delaying the turn-on of the second power supply through the programming of the UCD9222 so we bring all three signals, PMBUS_CNTL, EN1 and EN2, high at the same time.  You can tie EN1 and EN2 high and use just PMBUS_CNTL to enable the supply as well.

  • 0 in reply to Bill Taboada
    TI__Mastermind 46460 points

    I want to add some minor clarifications.  All of Bill's response above is correct.  The UCD9222 uses PMBUS_CNTL, EN1 and EN2 to enable power generation.  However, the EVM does not drive all three active simultaneously.  The PMBus_CNTL line is held high by a pull-up resistor.  Beta EVMs use a pull-up resistor within the FPGA.  Later PCB versions also have a pull-up resistor shown in the schematic so this requirement is more obvious.  The power sequencing logic in the FPGA then holds the EN1 and EN2 pins low to inhibit output and then drives them high to enable power conversion.  The current FPGA logic drives both EN1 and EN2 high at the same time.  The UCD9222 configuration adds the 5ms delay to the CVDD1 supply to meet the sequencing stated in the EVM documentation.

    Tom