TDA4VM: Low power manager

Zhang

davied zhang said:

  1 We want to start MCU Domain and MAIN Domain by spl. So need porting LPM to MCU1_0, what do we need to do?

For the very first time R5 SPL can come up on the device but when you go from ACTIVE -> MCU Only mode and then come back to ACTIVE mode, then you need to rely on the MCU R5F application to boot other cores, the R5 SPL will not come up as the MCU was alive and is not resetting. So you need the boot capability in your MCU R5F application. What you need to update is, instead of booting the kernel directly, if you want to have ATF, OPTEE, A72 SPL and u-boot in the mix, you need to boot them instead of the kernel from the MCU R5F application. Please note, this flow is not supported in the SDK.

Regards

Karan

HI,Karan

    Thanks for your support. Now we have decided on the way to use SPL, so we can't use lpm.

    1. We can use IO to cantrol power of peripheral of MAIN Domain.

     2. PM can cantrol power of cores(A72 R5F C66 C71) of MAIN Domain, not by PMIC.  Is this right?

     We want use 1+2 to release MAIN Domain poweroff and restart. Does this way work？if so, how to control power of cores of MAIN Domain in MCU1_0? 

Best Regards,

Zhang

Hi Zhang

davied zhang said:

    Thanks for your support. Now we have decided on the way to use SPL, so we can't use lpm.

You can use the LPM in that case but the caveat would be that after the MCU only -> Active mode transition, you would need the MCU R5F application to boot u-boot and then u-boot boots the other cores.

davied zhang said:

    1. We can use IO to cantrol power of peripheral of MAIN Domain.

Can you please elaborate here?

davied zhang said:

     2. PM can cantrol power of cores(A72 R5F C66 C71) of MAIN Domain, not by PMIC.  Is this right?

Do you mean, that PMIC would still provide power to the MAIN domain but you would turn off the PSCs for the cores? If the PMIC supplies power, the power savings with keeping cores powered off would not be much.

Can you please highlight what power envelope you are targeting during this low power mode?

Regards

Karan

Hi,Karan

       Thanks for your support.

Karan Saxena said:

Can you please elaborate here?

      1.We have added IO control to the peripheral power, so we can poweroff all peripheral bying IO.

Karan Saxena said:

Do you mean, that PMIC would still provide power to the MAIN domain but you would turn off the PSCs for the cores? If the PMIC supplies power, the power savings with keeping cores powered off would not be much.

    2.Yes,you are right.  We want PMIC would still provide power to the MAIN domain but turn off the PSCs for the cores.  how to control power of cores of MAIN Domain in MCU1_0? Is there an API in the SDK?

    3.Our current goal is to get down to 12v 500mA by using 1+2. And we go to  using MCU-only mode in the next stage.

Best Regards,

Zhang

Hi Zhang

davied zhang said:

    2.Yes,you are right.  We want PMIC would still provide power to the MAIN domain but turn off the PSCs for the cores.  how to control power of cores of MAIN Domain in MCU1_0? Is there an API in the SDK?

You can use the Sciclient APIs to reset the cores, you can review the SBL code for this. I'm assuming that you just want to keep the cores in reset and not doing anything right? Also, who loads them back when you need to be fully operational again?

Regards

Karan