AM6442: TCP/IP communication does not work properly with Ethernet communication using AM64 and DP83867

Conor said:

Q1
In the data sheet, RGMII is described as having multiple PINs MUXed together. However, another page provides definitions for combinations of use. Are port combinations other than IOSET in the data sheet not configurable? For example, is it possible to configure a combination like PRG0_PRU1_GPO7, RGMII1_RD1, PRG1_PRU1_GPO8 in RGMII1_RD0?

The note at the top of table 5 in the datasheet states that the Sysconfig tool should be used. 

The Sysconfig tool will help you understand  which combinations of peripherals can be supported by the device.  An online version is available here: https://dev.ti.com/sysconfig/#/start

Conor said:

Q2.
Is there a register to set IOSET other than I/O pin port settings?

IOSets define the valid combinations of interface pins that can be used in a design. Using pins not contained in a single IOSet may result issues with the interface functionality. IOSets are defined during the design of a device and are not programmable.

Are you using an EVM or a custom board?   If custom, does the RGMII interface use pins contained within a single IOSet? 

--Paul 

Hi Paul,

Thank you for your reply. I have three additional questions.

Q1.

PaulM said:

IOSets define the valid combinations of interface pins that can be used in a design.

Could you please tell me which IOSet is AM6442BSEFHAALV and AM6442BSDGHAALV?

Q2.
In table 7-35, could you please tell me what registers need to be set in order to use IOSET2, other than the corresponding input/output ports?

Q3.
In table 7-35, if all ports listed in IOSET1 and 2 are set to MUXMODE=4, which of IOSET1 and 2 has priority?

Thanks,

Conor

Conor said:

Could you please tell me which IOSet is AM6442BSEFHAALV and AM6442BSDGHAALV?

The IOSets will be the same on both devices 

Conor said:

In table 7-35, could you please tell me what registers need to be set in order to use IOSET2, other than the corresponding input/output ports?

There is no IOSET specific register that needs to be programmed.  All that is required is that the CPSW RGMII1 port uses pins from the same IOset and that padconfig register of the associated package balls be programmed with the correct mux mode. The Sysconfig tool will do this. 

Conor said:

In table 7-35, if all ports listed in IOSET1 and 2 are set to MUXMODE=4, which of IOSET1 and 2 has priority?

There is no priority. The each interface signal should only be mapped to the ball of the same IOset, and not more than one. In this case all IOSET1, or all IOSET2.  This is not a physical "switch", but rather a grouping of ball assignments.  A signal/ball mapping can appear in more than one IOset.

So for CPSW, Table 7-35,  RGMII1_TX_CTL has the same mapping in both IOSet1 and IOSet2, ie  PRG1_PRU0_GPO9.

However, RGMII1_RD3 has a different mapping for each IOSet.  in IOSE1 it maps to PRG0_PRU1_GPO7, but in IOSET2 it maps to PRG1_PRU1_GPO19. You should never set both balls to muxmode  4! Only one should be selected. The ball not selected can be used for one of the other possible muxed signals.

Again, the Sysconfig tool will handle this based on your inputs. 

--Paul 

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