TDA4VM: ETH PHY:no supported caps found

Hi,

Can you please confirm, are you using the TI EVM? or custom Board?

If custom Board what are the PHYs being used, whether PHY driver is added to enet or not? If not, please refer to PHY Integration Guide and intergrade your PHY drive to enet.

Also, please share the complete log of MCU2_0?

If you made any changes on top of release ethfw, please share for review?

Best Regards,
Sudheer

Hi,Sudheer

     Thanks for your support.

     Yes, it's on our custom board. The PHY we used is the same as TDA4VM EVM. The log of MCU2_0 as follows:

[MCU2_0] ETHFW Version   : 0.02.00
[MCU2_0]     13.843746 s: ETHFW Build Date: Dec 25, 2023
[MCU2_0]     13.843780 s: ETHFW Build Time: 13:51:46
[MCU2_0]     13.843807 s: ETHFW Commit SHA: 402d4744
[MCU2_0]     13.843876 s: ETHFW: Init ... DONE !!!
[MCU2_0]     13.843907 s: ETHFW: Remove server Init ... !!!
[MCU2_0]     13.844086 s: CpswProxyServer: Virtual port configuration:
[MCU2_0]     13.844138 s:   mpu_1_0 <-> Switch port 0: mpu_1_0_ethswitch-device-0
[MCU2_0]     13.844182 s:   mcu_2_1 <-> Switch port 1: mcu_2_1_ethswitch-device-1
[MCU2_0]     13.844223 s:   mpu_1_0 <-> MAC port 1: mpu_1_0_ethmac-device-1
[MCU2_0]     13.844262 s:   mcu_2_1 <-> MAC port 4: mcu_2_1_ethmac-device-4
[MCU2_0]     13.845299 s: CpswProxyServer: initialization completed (core: mcu2_0)
[MCU2_0]     13.845365 s: ETHFW: Remove server Init ... DONE !!!
[MCU2_0]     13.846520 s: Starting lwIP, local interface IP is dhcp-enabled
[MCU2_0]     13.854577 s: Host MAC address: 70:ff:76:1d:92:c3
[MCU2_0]     13.858866 s: [LWIPIF_LWIP] Enet LLD netif initialized successfully
[MCU2_0]     13.858960 s: Added interface 'ti1', IP is 0.0.0.0
[MCU2_0]     13.894655 s: FVID2: Init ... !!!
[MCU2_0]     13.894767 s: FVID2: Init ... Done !!!
[MCU2_0]     13.894823 s: DSS: Init ... !!!
[MCU2_0]     13.894851 s: DSS: Display type is eDP !!!
[MCU2_0]     13.894878 s: DSS: M2M Path is enabled !!!
[MCU2_0]     13.894904 s: DSS: SoC init ... !!!
[MCU2_0]     13.894926 s: SCICLIENT: Sciclient_pmSetModuleState module=152 state=2
[MCU2_0]     13.895201 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]     13.895246 s: SCICLIENT: Sciclient_pmSetModuleState module=297 state=2
[MCU2_0]     13.895450 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]     13.895482 s: SCICLIENT: Sciclient_pmSetModuleState module=151 state=2
[MCU2_0]     13.895730 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]     13.895780 s: SCICLIENT: Sciclient_pmSetModuleClkParent module=152 clk=9 parent=11
[MCU2_0]     13.895922 s: SCICLIENT: Sciclient_pmSetModuleClkParent success
[MCU2_0]     13.895959 s: SCICLIENT: Sciclient_pmSetModuleClkParent module=152 clk=13 parent=18
[MCU2_0]     13.896085 s: SCICLIENT: Sciclient_pmSetModuleClkParent success
[MCU2_0]     13.896119 s: SCICLIENT: Sciclient_pmSetModuleClkParent module=152 clk=1 parent=2
[MCU2_0]     13.896218 s: SCICLIENT: Sciclient_pmSetModuleClkParent success
[MCU2_0]     13.896251 s: SCICLIENT: Sciclient_pmSetModuleClkFreq module=152 clk=1 freq=148500000
[MCU2_0]     13.897678 s: SCICLIENT: Sciclient_pmSetModuleClkFreq success
[MCU2_0]     13.897732 s: SCICLIENT: Sciclient_pmModuleClkRequest module=152 clk=1 state=2 flag=0
[MCU2_0]     13.897904 s: SCICLIENT: Sciclient_pmModuleClkRequest success
[MCU2_0]     13.897942 s: DSS: SoC init ... Done !!!
[MCU2_0]     13.897968 s: DSS: Board init ... !!!
[MCU2_0]     13.897991 s: DSS: Board init ... Done !!!
[MCU2_0]     13.917868 s: DSS: Init ... Done !!!
[MCU2_0]     13.917935 s: VHWA: VPAC Init ... !!!
[MCU2_0]     13.917965 s: SCICLIENT: Sciclient_pmSetModuleState module=290 state=2
[MCU2_0]     13.918217 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]     13.918258 s: VHWA: LDC Init ... !!!
[MCU2_0]     13.922151 s: VHWA: LDC Init ... Done !!!
[MCU2_0]     13.922220 s: VHWA: MSC Init ... !!!
[MCU2_0]     13.935239 s: VHWA: MSC Init ... Done !!!
[MCU2_0]     13.935307 s: VHWA: NF Init ... !!!
[MCU2_0]     13.937352 s: VHWA: NF Init ... Done !!!
[MCU2_0]     13.937416 s: VHWA: VISS Init ... !!!
[MCU2_0]     13.949394 s: VHWA: VISS Init ... Done !!!
[MCU2_0]     13.949459 s: VHWA: VPAC Init ... Done !!!
[MCU2_0]     13.949506 s:  VX_ZONE_INIT:Enabled
[MCU2_0]     13.949538 s:  VX_ZONE_ERROR:Enabled
[MCU2_0]     13.949565 s:  VX_ZONE_WARNING:Enabled
[MCU2_0]     13.951296 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target MCU2-0 
[MCU2_0]     13.951574 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target VPAC_NF 
[MCU2_0]     13.952008 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target VPAC_LDC1 
[MCU2_0]     13.952264 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target VPAC_MSC1 
[MCU2_0]     13.952506 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target VPAC_MSC2 
[MCU2_0]     13.952924 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target VPAC_VISS1 
[MCU2_0]     13.953223 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target CAPTURE1 
[MCU2_0]     13.953492 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target CAPTURE2 
[MCU2_0]     13.953885 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target DISPLAY1 
[MCU2_0]     13.954181 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target DISPLAY2 
[MCU2_0]     13.954428 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target CSITX 
[MCU2_0]     13.954824 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target CAPTURE3 
[MCU2_0]     13.955127 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target CAPTURE4 
[MCU2_0]     13.955405 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target CAPTURE5 
[MCU2_0]     13.955784 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target CAPTURE6 
[MCU2_0]     13.956073 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target CAPTURE7 
[MCU2_0]     13.956349 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target CAPTURE8 
[MCU2_0]     13.956599 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target DSS_M2M1 
[MCU2_0]     13.957003 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target DSS_M2M2 
[MCU2_0]     13.957260 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target DSS_M2M3 
[MCU2_0]     13.957501 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target DSS_M2M4 
[MCU2_0]     13.957560 s:  VX_ZONE_INIT:[tivxInitLocal:130] Initialization Done !!!
[MCU2_0]     13.957596 s: APP: OpenVX Target kernel init ... !!!
[MCU2_0]     13.978906 s: APP: OpenVX Target kernel init ... Done !!!
[MCU2_0]     13.978972 s: CSI2RX: Init ... !!!
[MCU2_0]     13.979002 s: SCICLIENT: Sciclient_pmSetModuleState module=25 state=2
[MCU2_0]     13.979215 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]     13.979256 s: SCICLIENT: Sciclient_pmSetModuleState module=26 state=2
[MCU2_0]     13.979450 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]     13.979482 s: SCICLIENT: Sciclient_pmSetModuleState module=27 state=2
[MCU2_0]     13.979732 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]     13.979784 s: SCICLIENT: Sciclient_pmSetModuleState module=147 state=2
[MCU2_0]     13.979916 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]     13.979951 s: SCICLIENT: Sciclient_pmSetModuleState module=148 state=2
[MCU2_0]     13.980046 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]     13.980290 s: CSI2RX: Init ... Done !!!
[MCU2_0]     13.980328 s: CSI2TX: Init ... !!!
[MCU2_0]     13.980352 s: SCICLIENT: Sciclient_pmSetModuleState module=25 state=2
[MCU2_0]     13.980453 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]     13.980490 s: SCICLIENT: Sciclient_pmSetModuleState module=28 state=2
[MCU2_0]     13.980746 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]     13.980797 s: SCICLIENT: Sciclient_pmSetModuleState module=296 state=2
[MCU2_0]     13.980948 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]     13.981048 s: CSI2TX: Init ... Done !!!
[MCU2_0]     13.981083 s: ISS: Init ... !!!
[MCU2_0]     13.981122 s: IssSensor_Init ... Done !!!
[MCU2_0]     13.981202 s: IttRemoteServer_Init ... Done !!!
[MCU2_0]     13.981236 s: VISS REMOTE SERVICE: Init ... !!!
[MCU2_0]     13.981303 s: VISS REMOTE SERVICE: Init ... Done !!!
[MCU2_0]     13.981335 s: UDMA Copy: Init ... !!!
[MCU2_0]     13.983378 s: UDMA Copy: Init ... Done !!!
[MCU2_0]     13.983490 s: APP: Init ... Done !!!
[MCU2_0]     13.983529 s: APP: Run ... !!!
[MCU2_0]     13.983554 s: IPC: Starting echo test ...
[MCU2_0]     13.987419 s: APP: Run ... Done !!!
[MCU2_0]     13.989212 s: IPC: Echo status: mpu1_0[x] mcu2_0[s] mcu2_1[P] mcu3_0[.] mcu3_1[.] C66X_1[.] C66X_2[.] C7X_1[.] 
[MCU2_0]     13.989348 s: IPC: Echo status: mpu1_0[x] mcu2_0[s] mcu2_1[P] mcu3_0[P] mcu3_1[.] C66X_1[.] C66X_2[.] C7X_1[.] 
[MCU2_0]     13.989835 s: IPC: Echo status: mpu1_0[x] mcu2_0[s] mcu2_1[P] mcu3_0[P] mcu3_1[P] C66X_1[.] C66X_2[.] C7X_1[.] 
[MCU2_0]     13.989972 s: IPC: Echo status: mpu1_0[x] mcu2_0[s] mcu2_1[P] mcu3_0[P] mcu3_1[P] C66X_1[P] C66X_2[.] C7X_1[.] 
[MCU2_0]     13.990084 s: IPC: Echo status: mpu1_0[x] mcu2_0[s] mcu2_1[P] mcu3_0[P] mcu3_1[P] C66X_1[P] C66X_2[P] C7X_1[.] 
[MCU2_0]     13.990191 s: IPC: Echo status: mpu1_0[x] mcu2_0[s] mcu2_1[P] mcu3_0[P] mcu3_1[P] C66X_1[P] C66X_2[P] C7X_1[P] 
[MCU2_0]     14.017611 s: Function:CpswProxyServer_attachExtHandlerCb,HostId:0,CpswType:6
[MCU2_0]     14.078474 s: Function:CpswProxyServer_attachExtHandlerCb,HostId:0,CpswType:6
[MCU2_0]     14.141963 s: EnetPhy_enableState: PHY 12: no supported caps found
[MCU2_0]     14.142248 s: EnetPhy_enableState: PHY 0: no supported caps found
[MCU2_0]     14.142512 s: EnetPhy_enableState: PHY 3: no supported caps found
[MCU2_0]     14.142890 s: EnetPhy_enableState: PHY 15: no supported caps found
[MCU2_0]     14.241947 s: EnetPhy_enableState: PHY 12: no supported caps found
[MCU2_0]     14.242239 s: EnetPhy_enableState: PHY 0: no supported caps found
[MCU2_0]     14.242503 s: EnetPhy_enableState: PHY 3: no supported caps found
[MCU2_0]     14.242893 s: EnetPhy_enableState: PHY 15: no supported caps found
[MCU2_0]     14.341943 s: EnetPhy_enableState: PHY 12: no supported caps found
[MCU2_0]     14.342233 s: EnetPhy_enableState: PHY 0: no supported caps found
[MCU2_0]     14.342494 s: EnetPhy_enableState: PHY 3: no supported caps found
[MCU2_0]     14.342873 s: EnetPhy_enableState: PHY 15: no supported caps found
[MCU2_0]     14.441948 s: EnetPhy_enableState: PHY 12: no supported caps found
[MCU2_0]     14.442239 s: EnetPhy_enableState: PHY 0: no supported caps found
[MCU2_0]     14.442511 s: EnetPhy_enableState: PHY 3: no supported caps found
[MCU2_0]     14.442899 s: EnetPhy_enableState: PHY 15: no supported caps found
[MCU2_0]     14.541945 s: EnetPhy_enableState: PHY 12: no supported caps found
[MCU2_0]     14.542226 s: EnetPhy_enableState: PHY 0: no supported caps found
[MCU2_0]     14.542485 s: EnetPhy_enableState: PHY 3: no supported caps found
[MCU2_0]     14.542865 s: EnetPhy_enableState: PHY 15: no supported caps found
[MCU2_0]     14.641951 s: EnetPhy_enableState: PHY 12: no supported caps found
[MCU2_0]     14.642239 s: EnetPhy_enableState: PHY 0: no supported caps found
[MCU2_0]     14.642505 s: EnetPhy_enableState: PHY 3: no supported caps found
[MCU2_0]     14.642882 s: EnetPhy_enableState: PHY 15: no supported caps found
[MCU2_0]     14.741942 s: EnetPhy_enableState: PHY 12: no supported caps found
[MCU2_0]     14.742230 s: EnetPhy_enableState: PHY 0: no supported caps found
[MCU2_0]     14.742497 s: EnetPhy_enableState: PHY 3: no supported caps found
[MCU2_0]     14.742868 s: EnetPhy_enableState: PHY 15: no supported caps found
[MCU2_0]     14.841942 s: EnetPhy_enableState: PHY 12: no supported caps found
[MCU2_0]     14.842223 s: EnetPhy_enableState: PHY 0: no supported caps found
[MCU2_0]     14.842487 s: EnetPhy_enableState: PHY 3: no supported caps found
[MCU2_0]     14.842863 s: EnetPhy_enableState: PHY 15: no supported caps found
[MCU2_0]     14.941946 s: EnetPhy_enableState: PHY 12: no supported caps found
[MCU2_0]     14.942229 s: EnetPhy_enableState: PHY 0: no supported caps found
[MCU2_0]     14.942491 s: EnetPhy_enableState: PHY 3: no supported caps found
[MCU2_0]     14.942861 s: EnetPhy_enableState: PHY 15: no supported caps found
[MCU2_0]     15.041943 s: EnetPhy_enableState: PHY 12: no supported caps found
[MCU2_0]     15.042229 s: EnetPhy_enableState: PHY 0: no supported caps found
[MCU2_0]     15.042498 s: EnetPhy_enableState: PHY 3: no supported caps found
[MCU2_0]     15.042873 s: EnetPhy_enableState: PHY 15: no supported caps found
[MCU2_0]     15.078727 s: Assertion @ Line: 1212 in enet_mcm.c: false : failed !!!
[MCU2_0]     15.141946 s: EnetPhy_enableState: PHY 12: no supported caps found
[MCU2_0]     15.142232 s: EnetPhy_enableState: PHY 0: no supported caps found
[MCU2_0]     15.142492 s: EnetPhy_enableState: PHY 3: no supported caps found
[MCU2_0]     15.142872 s: EnetPhy_enableState: PHY 15: no supported caps found
[MCU2_0]     15.241936 s: EnetPhy_enableState: PHY 12: no supported caps found
[MCU2_0]     15.242218 s: EnetPhy_enableState: PHY 0: no supported caps found
[MCU2_0]     15.242479 s: EnetPhy_enableState: PHY 3: no supported caps found
[MCU2_0]     15.242860 s: EnetPhy_enableState: PHY 15: no supported caps found
[MCU2_0]     15.341930 s: EnetPhy_enableState: PHY 12: no supported caps found
[MCU2_0]     15.342217 s: EnetPhy_enableState: PHY 0: no supported caps found
[MCU2_0]     15.342478 s: EnetPhy_enableState: PHY 3: no supported caps found
[MCU2_0]     15.342854 s: EnetPhy_enableState: PHY 15: no supported caps found
[MCU2_0]     15.441942 s: EnetPhy_enableState: PHY 12: no supported caps found
[MCU2_0]     15.442224 s: EnetPhy_enableState: PHY 0: no supported caps found
[MCU2_0]     15.442487 s: EnetPhy_enableState: PHY 3: no supported caps found
[MCU2_0]     15.442864 s: EnetPhy_enableState: PHY 15: no supported caps found
[MCU2_0]     15.541944 s: EnetPhy_enableState: PHY 12: no supported caps found
[MCU2_0]     15.542230 s: EnetPhy_enableState: PHY 0: no supported caps found
[MCU2_0]     15.542492 s: EnetPhy_enableState: PHY 3: no supported caps found
[MCU2_0]     15.542873 s: EnetPhy_enableState: PHY 15: no supported caps found
[MCU2_0]     15.641939 s: EnetPhy_enableState: PHY 12: no supported caps found
[MCU2_0]     15.642219 s: EnetPhy_enableState: PHY 0: no supported caps found
[MCU2_0]     15.642480 s: EnetPhy_enableState: PHY 3: no supported caps found
[MCU2_0]     15.642856 s: EnetPhy_enableState: PHY 15: no supported caps found
[MCU2_0]     15.741941 s: EnetPhy_enableState: PHY 12: no supported caps found
[MCU2_0]     15.742226 s: EnetPhy_enableState: PHY 0: no supported caps found
[MCU2_0]     15.742490 s: EnetPhy_enableState: PHY 3: no supported caps found
[MCU2_0]     15.742867 s: EnetPhy_enableState: PHY 15: no supported caps found
[MCU2_0]     15.841934 s: EnetPhy_enableState: PHY 12: no supported caps found
[MCU2_0]     15.842220 s: EnetPhy_enableState: PHY 0: no supported caps found
[MCU2_0]     15.842485 s: EnetPhy_enableState: PHY 3: no supported caps found
[MCU2_0]     15.842859 s: EnetPhy_enableState: PHY 15: no supported caps found
[MCU2_0]     15.941949 s: EnetPhy_enableState: PHY 12: no supported caps found
[MCU2_0]     15.942235 s: EnetPhy_enableState: PHY 0: no supported caps found
[MCU2_0]    380.841936 s: EnetPhy_enableState: PHY 12: no supported caps found
[MCU2_0]    380.842217 s: EnetPhy_enableState: PHY 0: no supported caps found
[MCU2_0]    380.842485 s: EnetPhy_enableState: PHY 3: no supported caps found
[MCU2_0]    380.842862 s: EnetPhy_enableState: PHY 15: no supported caps found
[MCU2_0]    380.941942 s: EnetPhy_enableState: PHY 12: no supported caps found
[MCU2_0]    380.942230 s: EnetPhy_enableState: PHY 0: no supported caps found
[MCU2_0]    380.942496 s: EnetPhy_enableState: PHY 3: no supported caps found
[MCU2_0]    380.942863 s: EnetPhy_enableState: PHY 15: no supported caps found
[MCU2_0]    381.041938 s: EnetPhy_enableState: PHY 12: no supported caps found
[MCU2_0]    381.042224 s: EnetPhy_enableState: PHY 0: no supported caps found
[MCU2_0]    381.042487 s: EnetPhy_enableState: PHY 3: no supported caps found
[MCU2_0]    381.042866 s: EnetPhy_enableState: PHY 15: no supported caps found
[MCU2_0]    381.141932 s: EnetPhy_enableState: PHY 12: no supported caps found
[MCU2_0]    381.142218 s: EnetPhy_enableState: PHY 0: no supported caps found
[MCU2_0]    381.142484 s: EnetPhy_enableState: PHY 3: no supported caps found
[MCU2_0]    381.142857 s: EnetPhy_enableState: PHY 15: no supported caps found
[MCU2_0]    381.241936 s: EnetPhy_enableState: PHY 12: no supported caps found
[MCU2_0]    381.242222 s: EnetPhy_enableState: PHY 0: no supported caps found
[MCU2_0]    381.242483 s: EnetPhy_enableState: PHY 3: no supported caps found
[MCU2_0]    381.242855 s: EnetPhy_enableState: PHY 15: no supported caps found
[MCU2_0]    381.341935 s: EnetPhy_enableState: PHY 12: no supported caps found
[MCU2_0]    381.342219 s: EnetPhy_enableState: PHY 0: no supported caps found
[MCU2_0]    381.342482 s: EnetPhy_enableState: PHY 3: no supported caps found
[MCU2_0]    381.342853 s: EnetPhy_enableState: PHY 15: no supported caps found
[MCU2_0]    381.441941 s: EnetPhy_enableState: PHY 12: no supported caps found
[MCU2_0]    381.442228 s: EnetPhy_enableState: PHY 0: no supported caps found
[MCU2_0]    381.442491 s: EnetPhy_enableState: PHY 3: no supported caps found
[MCU2_0]    381.442869 s: EnetPhy_enableState: PHY 15: no supported caps found
[MCU2_0]    381.541936 s: EnetPhy_enableState: PHY 12: no supported caps found
[MCU2_0]    381.542218 s: EnetPhy_enableState: PHY 0: no supported caps found
[MCU2_0]    381.542483 s: EnetPhy_enableState: PHY 3: no supported caps found
[MCU2_0]    381.542856 s: EnetPhy_enableState: PHY 15: no supported caps found
[MCU2_0]    381.641936 s: EnetPhy_enableState: PHY 12: no supported caps found
[MCU2_0]    381.642221 s: EnetPhy_enableState: PHY 0: no supported caps found
[MCU2_0]    381.642483 s: EnetPhy_enableState: PHY 3: no supported caps found
[MCU2_0]    381.642849 s: EnetPhy_enableState: PHY 15: no supported caps found
[MCU2_0]    381.741939 s: EnetPhy_enableState: PHY 12: no supported caps found
[MCU2_0]    381.742224 s: EnetPhy_enableState: PHY 0: no supported caps found
[MCU2_0]    381.742486 s: EnetPhy_enableState: PHY 3: no supported caps found
[MCU2_0]    381.742864 s: EnetPhy_enableState: PHY 15: no supported caps found
[MCU2_0]    381.841940 s: EnetPhy_enableState: PHY 12: no supported caps found
[MCU2_0]    381.842225 s: EnetPhy_enableState: PHY 0: no supported caps found
[MCU2_0]    381.842488 s: EnetPhy_enableState: PHY 3: no supported caps found
[MCU2_0]    381.842863 s: EnetPhy_enableState: PHY 15: no supported caps found
[MCU2_0]    381.941944 s: EnetPhy_enableState: PHY 12: no supported caps found
[MCU2_0]    381.942227 s: EnetPhy_enableState: PHY 0: no supported caps found
[MCU2_0]    381.942485 s: EnetPhy_enableState: PHY 3: no supported caps found
[MCU2_0]    381.942860 s: EnetPhy_enableState: PHY 15: no supported caps found
[MCU2_0]    382.041939 s: EnetPhy_enableState: PHY 12: no supported caps found
[MCU2_0]    382.042225 s: EnetPhy_enableState: PHY 0: no supported caps found
[MCU2_0]    382.042488 s: EnetPhy_enableState: PHY 3: no supported caps found
[MCU2_0]    382.042864 s: EnetPhy_enableState: PHY 15: no supported caps found
[MCU2_0]    382.141941 s: EnetPhy_enableState: PHY 12: no supported caps found
[MCU2_0]    382.142226 s: EnetPhy_enableState: PHY 0: no supported caps found
[MCU2_0]    382.142487 s: EnetPhy_enableState: PHY 3: no supported caps found
[MCU2_0]    382.142862 s: EnetPhy_enableState: PHY 15: no supported caps found
[MCU2_0]    382.241940 s: EnetPhy_enableState: PHY 12: no supported caps found
[MCU2_0]    382.242221 s: EnetPhy_enableState: PHY 0: no supported caps found
[MCU2_0]    382.242483 s: EnetPhy_enableState: PHY 3: no supported caps found
[MCU2_0]    382.242858 s: EnetPhy_enableState: PHY 15: no supported caps found
[MCU2_0]    382.341935 s: EnetPhy_enableState: PHY 12: no supported caps found
[MCU2_0]    382.342217 s: EnetPhy_enableState: PHY 0: no supported caps found
[MCU2_0]    382.342474 s: EnetPhy_enableState: PHY 3: no supported caps found
[MCU2_0]    382.342839 s: EnetPhy_enableState: PHY 15: no supported caps found
[MCU2_0]    382.441945 s: EnetPhy_enableState: PHY 12: no supported caps found
[MCU2_0]    382.442231 s: EnetPhy_enableState: PHY 0: no supported caps found
[MCU2_0]    382.442495 s: EnetPhy_enableState: PHY 3: no supported caps found
[MCU2_0]    382.442864 s: EnetPhy_enableState: PHY 15: no supported caps found
[MCU2_0]    382.541937 s: EnetPhy_enableState: PHY 12: no supported caps found
[MCU2_0]    382.542221 s: EnetPhy_enableState: PHY 0: no supported caps found
[MCU2_0]    382.542485 s: EnetPhy_enableState: PHY 3: no supported caps found
[MCU2_0]    382.542860 s: EnetPhy_enableState: PHY 15: no supported caps found
[MCU2_0]    382.641941 s: EnetPhy_enableState: PHY 12: no supported caps found
[MCU2_0]    382.642222 s: EnetPhy_enableState: PHY 0: no supported caps found
[MCU2_0]    382.642487 s: EnetPhy_enableState: PHY 3: no supported caps found
[MCU2_0]    382.642856 s: EnetPhy_enableState: PHY 15: no supported caps found
[MCU2_0]    382.741939 s: EnetPhy_enableState: PHY 12: no supported caps found
[MCU2_0]    382.742220 s: EnetPhy_enableState: PHY 0: no supported caps found
[MCU2_0]    382.742481 s: EnetPhy_enableState: PHY 3: no supported caps found
[MCU2_0]    382.742853 s: EnetPhy_enableState: PHY 15: no supported caps found
[MCU2_1]      3.600020 s: CIO: Init ... Done !!!
[MCU2_1]      3.600094 s: ### CPU Frequency = 1000000000 Hz
[MCU2_1]      3.600134 s: CPU is running FreeRTOS
[MCU2_1]      3.600159 s: APP: Init ... !!!
[MCU2_1]      3.600182 s: SCICLIENT: Init ... !!!
[MCU2_1]      3.600444 s: SCICLIENT: DMSC FW version [8.6.3--v08.06.03 (Chill Capybar]
[MCU2_1]      3.600498 s: SCICLIENT: DMSC FW revision 0x8  
[MCU2_1]      3.600552 s: SCICLIENT: DMSC FW ABI revision 3.1
[MCU2_1]      3.600590 s: SCICLIENT: Init ... Done !!!
[MCU2_1]      3.600618 s: UDMA: Init ... !!!
[MCU2_1]      3.602307 s: UDMA: Init ... Done !!!
[MCU2_1]      3.602367 s: MEM: Init ... !!!
[MCU2_1]      3.602411 s: MEM: Created heap (DDR_LOCAL_MEM, id=0, flags=0x00000004) @ da000000 of size 16777216 bytes !!!
[MCU2_1]      3.602484 s: MEM: Created heap (L3_MEM, id=1, flags=0x00000001) @ 3640000 of size 262144 bytes !!!
[MCU2_1]      3.602562 s: MEM: Init ... Done !!!
[MCU2_1]      3.602589 s: IPC: Init ... !!!
[MCU2_1]      3.602651 s: IPC: 8 CPUs participating in IPC !!!
[MCU2_1]      3.602702 s: IPC: Waiting for HLOS to be ready ... !!!
[MCU2_1]     13.596402 s: IPC: HLOS is ready !!!
[MCU2_1]     13.617832 s: IPC: Init ... Done !!!
[MCU2_1]     13.617905 s: APP: Syncing with 7 CPUs ... !!!
[MCU2_1]     13.815489 s: APP: Syncing with 7 CPUs ... Done !!!
[MCU2_1]     13.815737 s: REMOTE_SERVICE: Init ... !!!
[MCU2_1]     13.817430 s: REMOTE_SERVICE: Init ... Done !!!
[MCU2_1]     13.817504 s: FVID2: Init ... !!!
[MCU2_1]     13.817591 s: FVID2: Init ... Done !!!
[MCU2_1]     13.817628 s: VHWA: DMPAC: Init ... !!!
[MCU2_1]     13.817657 s: SCICLIENT: Sciclient_pmSetModuleState module=48 state=2
[MCU2_1]     13.818246 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_1]     13.818286 s: SCICLIENT: Sciclient_pmSetModuleState module=305 state=2
[MCU2_1]     13.818823 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_1]     13.818865 s: VHWA: DOF Init ... !!!
[MCU2_1]     13.828454 s: VHWA: DOF Init ... Done !!!
[MCU2_1]     13.828535 s: VHWA: SDE Init ... !!!
[MCU2_1]     13.831323 s: VHWA: SDE Init ... Done !!!
[MCU2_1]     13.831385 s: VHWA: DMPAC: Init ... Done !!!
[MCU2_1]     13.831434 s:  VX_ZONE_INIT:Enabled
[MCU2_1]     13.831466 s:  VX_ZONE_ERROR:Enabled
[MCU2_1]     13.831493 s:  VX_ZONE_WARNING:Enabled
[MCU2_1]     13.832919 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target MCU2-1 
[MCU2_1]     13.833161 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target DMPAC_SDE 
[MCU2_1]     13.833387 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target DMPAC_DOF 
[MCU2_1]     13.833444 s:  VX_ZONE_INIT:[tivxInitLocal:130] Initialization Done !!!
[MCU2_1]     13.833481 s: APP: OpenVX Target kernel init ... !!!
[MCU2_1]     13.833783 s: APP: OpenVX Target kernel init ... Done !!!
[MCU2_1]     13.833829 s: UDMA Copy: Init ... !!!
[MCU2_1]     13.836306 s: UDMA Copy: Init ... Done !!!
[MCU2_1]     13.836397 s: APP: Init ... Done !!!
[MCU2_1]     13.836432 s: APP: Run ... !!!
[MCU2_1]     13.836458 s: IPC: Starting echo test ...
[MCU2_1]     13.839857 s: APP: Run ... Done !!!
[MCU2_1]     13.841528 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[s] mcu3_0[P] mcu3_1[.] C66X_1[.] C66X_2[.] C7X_1[.] 
[MCU2_1]     13.841668 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[s] mcu3_0[P] mcu3_1[P] C66X_1[.] C66X_2[.] C7X_1[.] 
[MCU2_1]     13.841778 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[s] mcu3_0[P] mcu3_1[P] C66X_1[P] C66X_2[.] C7X_1[.] 
[MCU2_1]     13.841882 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[s] mcu3_0[P] mcu3_1[P] C66X_1[P] C66X_2[P] C7X_1[.] 
[MCU2_1]     13.841982 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[s] mcu3_0[P] mcu3_1[P] C66X_1[P] C66X_2[P] C7X_1[P] 
[MCU2_1]     13.990566 s: IPC: Echo status: mpu1_0[x] mcu2_0[P] mcu2_1[s] mcu3_0[P] mcu3_1[P] C66X_1[P] C66X_2[P] C7X_1[P] 
[MCU3_0]      3.635334 s: CIO: Init ... Done !!!
[MCU3_0]      3.635399 s: ### CPU Frequency = 1000000000 Hz
[MCU3_0]      3.635440 s: CPU is running FreeRTOS
[MCU3_0]      3.635466 s: APP: Init ... !!!
[MCU3_0]      3.635490 s: SCICLIENT: Init ... !!!
[MCU3_0]      3.635763 s: SCICLIENT: DMSC FW version [8.6.3--v08.06.03 (Chill Capybar]
[MCU3_0]      3.635831 s: SCICLIENT: DMSC FW revision 0x8  
[MCU3_0]      3.635867 s: SCICLIENT: DMSC FW ABI revision 3.1
[MCU3_0]      3.635902 s: SCICLIENT: Init ... Done !!!
[MCU3_0]      3.635928 s: MEM: Init ... !!!
[MCU3_0]      3.635964 s: MEM: Created heap (DDR_LOCAL_MEM, id=0, flags=0x00000004) @ db000000 of size 8388608 bytes !!!
[MCU3_0]      3.636029 s: MEM: Init ... Done !!!
[MCU3_0]      3.636054 s: IPC: Init ... !!!
[MCU3_0]      3.636113 s: IPC: 8 CPUs participating in IPC !!!
[MCU3_0]      3.636166 s: IPC: Waiting for HLOS to be ready ... !!!
[MCU3_0]     13.713343 s: IPC: HLOS is ready !!!
[MCU3_0]     13.734591 s: IPC: Init ... Done !!!
[MCU3_0]     13.734659 s: APP: Syncing with 7 CPUs ... !!!
[MCU3_0]     13.815488 s: APP: Syncing with 7 CPUs ... Done !!!
[MCU3_0]     13.815536 s: REMOTE_SERVICE: Init ... !!!
[MCU3_0]     13.817533 s: REMOTE_SERVICE: Init ... Done !!!
[MCU3_0]     13.817609 s:  VX_ZONE_INIT:Enabled
[MCU3_0]     13.817638 s:  VX_ZONE_ERROR:Enabled
[MCU3_0]     13.817663 s:  VX_ZONE_WARNING:Enabled
[MCU3_0]     13.818974 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target MCU3-0 
[MCU3_0]     13.819040 s:  VX_ZONE_INIT:[tivxInitLocal:130] Initialization Done !!!
[MCU3_0]     13.819077 s: APP: OpenVX Target kernel init ... !!!
[MCU3_0]     13.819107 s: APP: OpenVX Target kernel init ... Done !!!
[MCU3_0]     13.819136 s: APP: Init ... Done !!!
[MCU3_0]     13.819162 s: APP: Run ... !!!
[MCU3_0]     13.819184 s: IPC: Starting echo test ...
[MCU3_0]     13.822578 s: APP: Run ... Done !!!
[MCU3_0]     13.824225 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[s] mcu3_1[.] C66X_1[.] C66X_2[x] C7X_1[P] 
[MCU3_0]     13.824590 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[s] mcu3_1[.] C66X_1[P] C66X_2[.] C7X_1[P] 
[MCU3_0]     13.824797 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[s] mcu3_1[.] C66X_1[P] C66X_2[P] C7X_1[P] 
[MCU3_0]     13.824942 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[s] mcu3_1[P] C66X_1[P] C66X_2[P] C7X_1[P] 
[MCU3_0]     13.840656 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[P] mcu3_0[s] mcu3_1[P] C66X_1[P] C66X_2[P] C7X_1[P] 
[MCU3_0]     13.990589 s: IPC: Echo status: mpu1_0[x] mcu2_0[P] mcu2_1[P] mcu3_0[s] mcu3_1[P] C66X_1[P] C66X_2[P] C7X_1[P] 
[MCU3_1]      3.672590 s: CIO: Init ... Done !!!
[MCU3_1]      3.672657 s: ### CPU Frequency = 1000000000 Hz
[MCU3_1]      3.672701 s: CPU is running FreeRTOS
[MCU3_1]      3.672730 s: APP: Init ... !!!
[MCU3_1]      3.672755 s: SCICLIENT: Init ... !!!
[MCU3_1]      3.673005 s: SCICLIENT: DMSC FW version [8.6.3--v08.06.03 (Chill Capybar]
[MCU3_1]      3.673057 s: SCICLIENT: DMSC FW revision 0x8  
[MCU3_1]      3.673092 s: SCICLIENT: DMSC FW ABI revision 3.1
[MCU3_1]      3.673143 s: SCICLIENT: Init ... Done !!!
[MCU3_1]      3.673171 s: MEM: Init ... !!!
[MCU3_1]      3.673209 s: MEM: Created heap (DDR_LOCAL_MEM, id=0, flags=0x00000004) @ db800000 of size 8388608 bytes !!!
[MCU3_1]      3.673274 s: MEM: Init ... Done !!!
[MCU3_1]      3.673299 s: IPC: Init ... !!!
[MCU3_1]      3.673358 s: IPC: 8 CPUs participating in IPC !!!
[MCU3_1]      3.673407 s: IPC: Waiting for HLOS to be ready ... !!!
[MCU3_1]     13.794236 s: IPC: HLOS is ready !!!
[MCU3_1]     13.815376 s: IPC: Init ... Done !!!
[MCU3_1]     13.815441 s: APP: Syncing with 7 CPUs ... !!!
[MCU3_1]     13.815488 s: APP: Syncing with 7 CPUs ... Done !!!
[MCU3_1]     13.815524 s: REMOTE_SERVICE: Init ... !!!
[MCU3_1]     13.817530 s: REMOTE_SERVICE: Init ... Done !!!
[MCU3_1]     13.817610 s:  VX_ZONE_INIT:Enabled
[MCU3_1]     13.817643 s:  VX_ZONE_ERROR:Enabled
[MCU3_1]     13.817671 s:  VX_ZONE_WARNING:Enabled
[MCU3_1]     13.818978 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target MCU3-1 
[MCU3_1]     13.819038 s:  VX_ZONE_INIT:[tivxInitLocal:130] Initialization Done !!!
[MCU3_1]     13.819073 s: APP: OpenVX Target kernel init ... !!!
[MCU3_1]     13.819116 s: APP: OpenVX Target kernel init ... Done !!!
[MCU3_1]     13.819148 s: APP: Init ... Done !!!
[MCU3_1]     13.819175 s: APP: Run ... !!!
[MCU3_1]     13.819198 s: IPC: Starting echo test ...
[MCU3_1]     13.822613 s: APP: Run ... Done !!!
[MCU3_1]     13.823729 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[.] mcu3_1[s] C66X_1[.] C66X_2[x] C7X_1[P] 
[MCU3_1]     13.824535 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[s] C66X_1[.] C66X_2[.] C7X_1[P] 
[MCU3_1]     13.824660 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[s] C66X_1[P] C66X_2[.] C7X_1[P] 
[MCU3_1]     13.824903 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[s] C66X_1[P] C66X_2[P] C7X_1[P] 
[MCU3_1]     13.840677 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[P] mcu3_0[P] mcu3_1[s] C66X_1[P] C66X_2[P] C7X_1[P] 
[MCU3_1]     13.990612 s: IPC: Echo status: mpu1_0[x] mcu2_0[P] mcu2_1[P] mcu3_0[P] mcu3_1[s] C66X_1[P] C66X_2[P] C7X_1[P] 
[C6x_1 ]      3.719019 s: CIO: Init ... Done !!!
[C6x_1 ]      3.719045 s: ### CPU Frequency = 1350000000 Hz
[C6x_1 ]      3.719056 s: CPU is running FreeRTOS
[C6x_1 ]      3.719063 s: APP: Init ... !!!
[C6x_1 ]      3.719071 s: SCICLIENT: Init ... !!!
[C6x_1 ]      3.719301 s: SCICLIENT: DMSC FW version [8.6.3--v08.06.03 (Chill Capybar]
[C6x_1 ]      3.719313 s: SCICLIENT: DMSC FW revision 0x8  
[C6x_1 ]      3.719322 s: SCICLIENT: DMSC FW ABI revision 3.1
[C6x_1 ]      3.719332 s: SCICLIENT: Init ... Done !!!
[C6x_1 ]      3.719341 s: UDMA: Init ... !!!
[C6x_1 ]      3.721036 s: UDMA: Init ... Done !!!
[C6x_1 ]      3.721055 s: MEM: Init ... !!!
[C6x_1 ]      3.721067 s: MEM: Created heap (DDR_LOCAL_MEM, id=0, flags=0x00000004) @ dc000000 of size 16777216 bytes !!!
[C6x_1 ]      3.721085 s: MEM: Created heap (L2_MEM, id=2, flags=0x00000001) @ 800000 of size 229376 bytes !!!
[C6x_1 ]      3.721100 s: MEM: Created heap (DDR_SCRATCH_MEM, id=4, flags=0x00000001) @ dd000000 of size 50331648 bytes !!!
[C6x_1 ]      3.721116 s: MEM: Init ... Done !!!
[C6x_1 ]      3.721124 s: IPC: Init ... !!!
[C6x_1 ]      3.721146 s: IPC: 8 CPUs participating in IPC !!!
[C6x_1 ]      3.721159 s: IPC: Waiting for HLOS to be ready ... !!!
[C6x_1 ]     12.700339 s: IPC: HLOS is ready !!!
[C6x_1 ]     12.705202 s: IPC: Init ... Done !!!
[C6x_1 ]     12.705232 s: APP: Syncing with 7 CPUs ... !!!
[C6x_1 ]     13.815487 s: APP: Syncing with 7 CPUs ... Done !!!
[C6x_1 ]     13.815501 s: REMOTE_SERVICE: Init ... !!!
[C6x_1 ]     13.816234 s: REMOTE_SERVICE: Init ... Done !!!
[C6x_1 ]     13.816268 s:  VX_ZONE_INIT:Enabled
[C6x_1 ]     13.816278 s:  VX_ZONE_ERROR:Enabled
[C6x_1 ]     13.816288 s:  VX_ZONE_WARNING:Enabled
[C6x_1 ]     13.817153 s:  VX_ZONE_INIT:[tivxInitLocal:130] Initialization Done !!!
[C6x_1 ]     13.817168 s: APP: OpenVX Target kernel init ... !!!
[C6x_1 ]     13.817426 s: APP: OpenVX Target kernel init ... Done !!!
[C6x_1 ]     13.817442 s: UDMA Copy: Init ... !!!
[C6x_1 ]     13.821847 s: UDMA Copy: Init ... Done !!!
[C6x_1 ]     13.821869 s: APP: Init ... Done !!!
[C6x_1 ]     13.821877 s: APP: Run ... !!!
[C6x_1 ]     13.821886 s: IPC: Starting echo test ...
[C6x_1 ]     13.823398 s: APP: Run ... Done !!!
[C6x_1 ]     13.823806 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[.] mcu3_1[.] C66X_1[s] C66X_2[x] C7X_1[P] 
[C6x_1 ]     13.824076 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[.] C66X_1[s] C66X_2[.] C7X_1[P] 
[C6x_1 ]     13.824264 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[.] C66X_1[s] C66X_2[P] C7X_1[P] 
[C6x_1 ]     13.824398 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[P] C66X_1[s] C66X_2[P] C7X_1[P] 
[C6x_1 ]     13.840512 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[P] mcu3_0[P] mcu3_1[P] C66X_1[s] C66X_2[P] C7X_1[P] 
[C6x_1 ]     13.990585 s: IPC: Echo status: mpu1_0[x] mcu2_0[P] mcu2_1[P] mcu3_0[P] mcu3_1[P] C66X_1[s] C66X_2[P] C7X_1[P] 
[C6x_2 ]      3.804144 s: CIO: Init ... Done !!!
[C6x_2 ]      3.804171 s: ### CPU Frequency = 1350000000 Hz
[C6x_2 ]      3.804182 s: CPU is running FreeRTOS
[C6x_2 ]      3.804190 s: APP: Init ... !!!
[C6x_2 ]      3.804197 s: SCICLIENT: Init ... !!!
[C6x_2 ]      3.804431 s: SCICLIENT: DMSC FW version [8.6.3--v08.06.03 (Chill Capybar]
[C6x_2 ]      3.804444 s: SCICLIENT: DMSC FW revision 0x8  
[C6x_2 ]      3.804453 s: SCICLIENT: DMSC FW ABI revision 3.1
[C6x_2 ]      3.804464 s: SCICLIENT: Init ... Done !!!
[C6x_2 ]      3.804473 s: UDMA: Init ... !!!
[C6x_2 ]      3.806225 s: UDMA: Init ... Done !!!
[C6x_2 ]      3.806244 s: MEM: Init ... !!!
[C6x_2 ]      3.806258 s: MEM: Created heap (DDR_LOCAL_MEM, id=0, flags=0x00000004) @ e0000000 of size 16777216 bytes !!!
[C6x_2 ]      3.806276 s: MEM: Created heap (L2_MEM, id=2, flags=0x00000001) @ 800000 of size 229376 bytes !!!
[C6x_2 ]      3.806292 s: MEM: Created heap (DDR_SCRATCH_MEM, id=4, flags=0x00000001) @ e1000000 of size 50331648 bytes !!!
[C6x_2 ]      3.806308 s: MEM: Init ... Done !!!
[C6x_2 ]      3.806316 s: IPC: Init ... !!!
[C6x_2 ]      3.806339 s: IPC: 8 CPUs participating in IPC !!!
[C6x_2 ]      3.806354 s: IPC: Waiting for HLOS to be ready ... !!!
[C6x_2 ]     12.924563 s: IPC: HLOS is ready !!!
[C6x_2 ]     12.928983 s: IPC: Init ... Done !!!
[C6x_2 ]     12.929011 s: APP: Syncing with 7 CPUs ... !!!
[C6x_2 ]     13.815487 s: APP: Syncing with 7 CPUs ... Done !!!
[C6x_2 ]     13.815502 s: REMOTE_SERVICE: Init ... !!!
[C6x_2 ]     13.816238 s: REMOTE_SERVICE: Init ... Done !!!
[C6x_2 ]     13.816273 s:  VX_ZONE_INIT:Enabled
[C6x_2 ]     13.816284 s:  VX_ZONE_ERROR:Enabled
[C6x_2 ]     13.816295 s:  VX_ZONE_WARNING:Enabled
[C6x_2 ]     13.817157 s:  VX_ZONE_INIT:[tivxInitLocal:130] Initialization Done !!!
[C6x_2 ]     13.817172 s: APP: OpenVX Target kernel init ... !!!
[C6x_2 ]     13.817432 s: APP: OpenVX Target kernel init ... Done !!!
[C6x_2 ]     13.817449 s: UDMA Copy: Init ... !!!
[C6x_2 ]     13.822235 s: UDMA Copy: Init ... Done !!!
[C6x_2 ]     13.822260 s: APP: Init ... Done !!!
[C6x_2 ]     13.822269 s: APP: Run ... !!!
[C6x_2 ]     13.822278 s: IPC: Starting echo test ...
[C6x_2 ]     13.823835 s: APP: Run ... Done !!!
[C6x_2 ]     13.824260 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[.] mcu3_1[.] C66X_1[.] C66X_2[s] C7X_1[P] 
[C6x_2 ]     13.824299 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[.] mcu3_1[.] C66X_1[P] C66X_2[s] C7X_1[P] 
[C6x_2 ]     13.824402 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[.] C66X_1[P] C66X_2[s] C7X_1[P] 
[C6x_2 ]     13.824451 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[P] C66X_1[P] C66X_2[s] C7X_1[P] 
[C6x_2 ]     13.840563 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[P] mcu3_0[P] mcu3_1[P] C66X_1[P] C66X_2[s] C7X_1[P] 
[C6x_2 ]     13.990609 s: IPC: Echo status: mpu1_0[x] mcu2_0[P] mcu2_1[P] mcu3_0[P] mcu3_1[P] C66X_1[P] C66X_2[s] C7X_1[P] 
[C7x_1 ]      4.031819 s: CIO: Init ... Done !!!
[C7x_1 ]      4.031834 s: ### CPU Frequency = 1000000000 Hz
[C7x_1 ]      4.031844 s: CPU is running FreeRTOS
[C7x_1 ]      4.031852 s: APP: Init ... !!!
[C7x_1 ]      4.031860 s: SCICLIENT: Init ... !!!
[C7x_1 ]      4.032102 s: SCICLIENT: DMSC FW version [8.6.3--v08.06.03 (Chill Capybar]
[C7x_1 ]      4.032116 s: SCICLIENT: DMSC FW revision 0x8  
[C7x_1 ]      4.032126 s: SCICLIENT: DMSC FW ABI revision 3.1
[C7x_1 ]      4.032136 s: SCICLIENT: Init ... Done !!!
[C7x_1 ]      4.032145 s: UDMA: Init ... !!!
[C7x_1 ]      4.033477 s: UDMA: Init ... Done !!!
[C7x_1 ]      4.033489 s: MEM: Init ... !!!
[C7x_1 ]      4.033499 s: MEM: Created heap (DDR_LOCAL_MEM, id=0, flags=0x00000004) @ 117000000 of size 268435456 bytes !!!
[C7x_1 ]      4.033518 s: MEM: Created heap (L3_MEM, id=1, flags=0x00000001) @ 70020000 of size 8159232 bytes !!!
[C7x_1 ]      4.033536 s: MEM: Created heap (L2_MEM, id=2, flags=0x00000001) @ 64800000 of size 458752 bytes !!!
[C7x_1 ]      4.033553 s: MEM: Created heap (L1_MEM, id=3, flags=0x00000001) @ 64e00000 of size 16384 bytes !!!
[C7x_1 ]      4.033570 s: MEM: Created heap (DDR_SCRATCH_MEM, id=4, flags=0x00000001) @ 100000000 of size 385875968 bytes !!!
[C7x_1 ]      4.033588 s: MEM: Init ... Done !!!
[C7x_1 ]      4.033596 s: IPC: Init ... !!!
[C7x_1 ]      4.033609 s: IPC: 8 CPUs participating in IPC !!!
[C7x_1 ]      4.033622 s: IPC: Waiting for HLOS to be ready ... !!!
[C7x_1 ]     13.191703 s: IPC: HLOS is ready !!!
[C7x_1 ]     13.194221 s: IPC: Init ... Done !!!
[C7x_1 ]     13.194235 s: APP: Syncing with 7 CPUs ... !!!
[C7x_1 ]     13.815489 s: APP: Syncing with 7 CPUs ... Done !!!
[C7x_1 ]     13.815506 s: REMOTE_SERVICE: Init ... !!!
[C7x_1 ]     13.815673 s: REMOTE_SERVICE: Init ... Done !!!
[C7x_1 ]     13.815695 s:  VX_ZONE_INIT:Enabled
[C7x_1 ]     13.815705 s:  VX_ZONE_ERROR:Enabled
[C7x_1 ]     13.815715 s:  VX_ZONE_WARNING:Enabled
[C7x_1 ]     13.815873 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-1 
[C7x_1 ]     13.815937 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-1_PRI_2 
[C7x_1 ]     13.816035 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-1_PRI_3 
[C7x_1 ]     13.816144 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-1_PRI_4 
[C7x_1 ]     13.816240 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-1_PRI_5 
[C7x_1 ]     13.816311 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-1_PRI_6 
[C7x_1 ]     13.816423 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-1_PRI_7 
[C7x_1 ]     13.816498 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-1_PRI_8 
[C7x_1 ]     13.816520 s:  VX_ZONE_INIT:[tivxInitLocal:130] Initialization Done !!!
[C7x_1 ]     13.816533 s: APP: OpenVX Target kernel init ... !!!
[C7x_1 ]     13.816680 s: APP: OpenVX Target kernel init ... Done !!!
[C7x_1 ]     13.816695 s: APP: Init ... Done !!!
[C7x_1 ]     13.816704 s: APP: Run ... !!!
[C7x_1 ]     13.816713 s: IPC: Starting echo test ...
[C7x_1 ]     13.816933 s: APP: Run ... Done !!!
[C7x_1 ]     13.823741 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[.] C66X_1[.] C66X_2[x] C7X_1[s] 
[C7x_1 ]     13.823799 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[.] C66X_1[P] C66X_2[x] C7X_1[s] 
[C7x_1 ]     13.824190 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[.] C66X_1[P] C66X_2[P] C7X_1[s] 
[C7x_1 ]     13.824353 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[P] C66X_1[P] C66X_2[P] C7X_1[s] 
[C7x_1 ]     13.840593 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[P] mcu3_0[P] mcu3_1[P] C66X_1[P] C66X_2[P] C7X_1[s] 
[C7x_1 ]     13.990636 s: IPC: Echo status: mpu1_0[x] mcu2_0[P] mcu2_1[P] mcu3_0[P] mcu3_1[P] C66X_1[P] C66X_2[P] C7X_1[s] 
[MCU2_0]    382.841937 s: EnetPhy_enableState: PHY 12: no supported caps found
[MCU2_0]    382.842221 s: EnetPhy_enableState: PHY 0: no supported caps found
[MCU2_0]    382.842485 s: EnetPhy_enableState: PHY 3: no supported caps found
[MCU2_0]    382.842856 s: EnetPhy_enableState: PHY 15: no supported caps found
[MCU2_0]    382.941940 s: EnetPhy_enableState: PHY 12: no supported caps found
[MCU2_0]    382.942223 s: EnetPhy_enableState: PHY 0: no supported caps found

   We have modify mac-only port from port1/4 to port port6/7.  That's the only change we made on the ethfw.  Changes on file as follows:

    board-support/linux-5.10.162+gitAUTOINC+76b3e88d56-g76b3e88d56/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts

	cpsw9g_virt_maconly: main-r5fss-cpsw9g-virt-mac1 {
	cpsw9g_virt_maconly: main-r5fss-cpsw9g-virt-mac6 {
		compatible = "ti,j721e-cpsw-virt-mac";
		dma-coherent;
		ti,psil-base = <0x4a00>;
		ti,remote-name = "mpu_1_0_ethmac-device-1";
		ti,remote-name = "mpu_1_0_ethmac-device-6";

		dmas = <&main_udmap 0xca00>,
		       <&main_udmap 0xca01>,

vision_apps/utils/ethfw/src/app_ethfw_freertos.c

vision_apps/utils/ethfw/src/app_ethfw_tirtos.c

vision_apps/utils/ethfw/src/concerto.mak

Best Regards,

Zhang

Hi,

From below EthFw log it seems like still Port-1 & Port-4 only configured as MAC only Ports.
[MCU2_0] 13.844223 s: mpu_1_0 <-> MAC port 1: mpu_1_0_ethmac-device-1
[MCU2_0] 13.844262 s: mcu_2_1 <-> MAC port 4: mcu_2_1_ethmac-device-4

As you are using Vision apps.
Can you please confirm, have you followed for vision apps User Guide for building the application, and SD card preparation.

Best Regards,
Sudheer

Hi,Sudheer

    Thanks for your support.

Doredla Sudheer Kumar said:

From below EthFw log it seems like still Port-1 & Port-4 only configured as MAC only Ports.

    We got the LOG wrong before, the log of modified as follows:

root@j7-evm:/opt/vision_apps# source ./vision_apps_init.sh 
root@j7-evm:/opt/vision_apps# [MCU2_0]      3.869061 s: CIO: Init ... Done !!!
[MCU2_0]      3.869131 s: ### CPU Frequency = 1000000000 Hz
[MCU2_0]      3.869173 s: CPU is running FreeRTOS
[MCU2_0]      3.869197 s: APP: Init ... !!!
[MCU2_0]      3.869219 s: SCICLIENT: Init ... !!!
[MCU2_0]      3.869483 s: SCICLIENT: DMSC FW version [8.6.3--v08.06.03 (Chill Capybar]
[MCU2_0]      3.869534 s: SCICLIENT: DMSC FW revision 0x8  
[MCU2_0]      3.869566 s: SCICLIENT: DMSC FW ABI revision 3.1
[MCU2_0]      3.869602 s: SCICLIENT: Init ... Done !!!
[MCU2_0]      3.869628 s: UDMA: Init ... !!!
[MCU2_0]      3.871339 s: UDMA: Init ... Done !!!
[MCU2_0]      3.871399 s: MEM: Init ... !!!
[MCU2_0]      3.871440 s: MEM: Created heap (DDR_LOCAL_MEM, id=0, flags=0x00000004) @ d9000000 of size 16777216 bytes !!!
[MCU2_0]      3.871516 s: MEM: Created heap (L3_MEM, id=1, flags=0x00000000) @ 3600000 of size 262144 bytes !!!
[MCU2_0]      3.871577 s: MEM: Init ... Done !!!
[MCU2_0]      3.871602 s: IPC: Init ... !!!
[MCU2_0]      3.871662 s: IPC: 8 CPUs participating in IPC !!!
[MCU2_0]      3.871710 s: IPC: Waiting for HLOS to be ready ... !!!
[MCU2_0]     13.534331 s: IPC: HLOS is ready !!!
[MCU2_0]     13.555524 s: IPC: Init ... Done !!!
[MCU2_0]     13.555588 s: APP: Syncing with 7 CPUs ... !!!
[MCU2_0]     14.227416 s: APP: Syncing with 7 CPUs ... Done !!!
[MCU2_0]     14.227648 s: REMOTE_SERVICE: Init ... !!!
[MCU2_0]     14.229365 s: REMOTE_SERVICE: Init ... Done !!!
[MCU2_0]     14.229431 s: ETHFW: Init ... !!!
[MCU2_0]     14.337461 s: Warning: Using 6 MAC address(es) from static pool
[MCU2_0]     14.337573 s: ETHFW: Shared multicasts (software fanout):
[MCU2_0]     14.337618 s: ETHFW: Reserved multicasts:
[MCU2_0]     14.337645 s:   01:80:c2:00:00:0e
[MCU2_0]     14.337690 s:   01:1b:19:00:00:00
[MCU2_0]     14.337934 s: EnetMcm: CPSW_9G on MAIN NAVSS
[MCU2_0]     14.345371 s: Mdio_open: MDIO manual mode enabled
[MCU2_0]     14.348041 s: PHY 0 is alive
[MCU2_0]     14.348330 s: PHY 3 is alive
[MCU2_0]     14.348973 s: PHY 12 is alive
[MCU2_0]     14.350655 s: EnetPhy_bindDriver: PHY 12: OUI:080028 Model:23 Ver:01 <-> 'dp83867' : OK
[MCU2_0]     14.351161 s: EnetPhy_bindDriver: PHY 0: OUI:080028 Model:23 Ver:01 <-> 'dp83867' : OK
[MCU2_0]     14.351640 s: EnetPhy_bindDriver: PHY 3: OUI:080028 Model:23 Ver:01 <-> 'dp83867' : OK
[MCU2_0]     14.354204 s: 
[MCU2_0] ETHFW Version   : 0.02.00
[MCU2_0]     14.354280 s: ETHFW Build Date: Jan  8, 2024
[MCU2_0]     14.354314 s: ETHFW Build Time: 19:40:53
[MCU2_0]     14.354340 s: ETHFW Commit SHA: 5994a127
[MCU2_0]     14.354409 s: ETHFW: Init ... DONE !!!
[MCU2_0]     14.354441 s: ETHFW: Remove server Init ... !!!
[MCU2_0]     14.354622 s: CpswProxyServer: Virtual port configuration:
[MCU2_0]     14.354673 s:   mpu_1_0 <-> Switch port 0: mpu_1_0_ethswitch-device-0
[MCU2_0]     14.354716 s:   mcu_2_1 <-> Switch port 1: mcu_2_1_ethswitch-device-1
[MCU2_0]     14.354756 s:   mpu_1_0 <-> MAC port 6: mpu_1_0_ethmac-device-6
[MCU2_0]     14.354809 s:   mcu_2_1 <-> MAC port 7: mcu_2_1_ethmac-device-7
[MCU2_0]     14.355844 s: CpswProxyServer: initialization completed (core: mcu2_0)
[MCU2_0]     14.355911 s: ETHFW: Remove server Init ... DONE !!!
[MCU2_0]     14.357092 s: Starting lwIP, local interface IP is dhcp-enabled
[MCU2_0]     14.365248 s: Host MAC address: 70:ff:76:1d:92:c3
[MCU2_0]     14.369500 s: [LWIPIF_LWIP] Enet LLD netif initialized successfully
[MCU2_0]     14.369595 s: Added interface 'ti1', IP is 0.0.0.0
[MCU2_0]     14.405796 s: FVID2: Init ... !!!
[MCU2_0]     14.405911 s: FVID2: Init ... Done !!!
[MCU2_0]     14.405966 s: DSS: Init ... !!!
[MCU2_0]     14.405993 s: DSS: Display type is eDP !!!
[MCU2_0]     14.406020 s: DSS: M2M Path is enabled !!!
[MCU2_0]     14.406046 s: DSS: SoC init ... !!!
[MCU2_0]     14.406068 s: SCICLIENT: Sciclient_pmSetModuleState module=152 state=2
[MCU2_0]     14.406328 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]     14.406370 s: SCICLIENT: Sciclient_pmSetModuleState module=297 state=2
[MCU2_0]     14.406571 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]     14.406606 s: SCICLIENT: Sciclient_pmSetModuleState module=151 state=2
[MCU2_0]     14.406876 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]     14.406931 s: SCICLIENT: Sciclient_pmSetModuleClkParent module=152 clk=9 parent=11
[MCU2_0]     14.407084 s: SCICLIENT: Sciclient_pmSetModuleClkParent success
[MCU2_0]     14.407120 s: SCICLIENT: Sciclient_pmSetModuleClkParent module=152 clk=13 parent=18
[MCU2_0]     14.407247 s: SCICLIENT: Sciclient_pmSetModuleClkParent success
[MCU2_0]     14.407280 s: SCICLIENT: Sciclient_pmSetModuleClkParent module=152 clk=1 parent=2
[MCU2_0]     14.407386 s: SCICLIENT: Sciclient_pmSetModuleClkParent success
[MCU2_0]     14.407419 s: SCICLIENT: Sciclient_pmSetModuleClkFreq module=152 clk=1 freq=148500000
[MCU2_0]     14.408820 s: SCICLIENT: Sciclient_pmSetModuleClkFreq success
[MCU2_0]     14.408871 s: SCICLIENT: Sciclient_pmModuleClkRequest module=152 clk=1 state=2 flag=0
[MCU2_0]     14.409040 s: SCICLIENT: Sciclient_pmModuleClkRequest success
[MCU2_0]     14.409079 s: DSS: SoC init ... Done !!!
[MCU2_0]     14.409107 s: DSS: Board init ... !!!
[MCU2_0]     14.409130 s: DSS: Board init ... Done !!!
[MCU2_0]     14.429009 s: DSS: Init ... Done !!!
[MCU2_0]     14.429075 s: VHWA: VPAC Init ... !!!
[MCU2_0]     14.429106 s: SCICLIENT: Sciclient_pmSetModuleState module=290 state=2
[MCU2_0]     14.429353 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]     14.429394 s: VHWA: LDC Init ... !!!
[MCU2_0]     14.432854 s: Function:CpswProxyServer_attachExtHandlerCb,HostId:0,CpswType:6
[MCU2_0]     14.433510 s: VHWA: LDC Init ... Done !!!
[MCU2_0]     14.433569 s: VHWA: MSC Init ... !!!
[MCU2_0]     14.446873 s: VHWA: MSC Init ... Done !!!
[MCU2_0]     14.446944 s: VHWA: NF Init ... !!!
[MCU2_0]     14.449078 s: VHWA: NF Init ... Done !!!
[MCU2_0]     14.449141 s: VHWA: VISS Init ... !!!
[MCU2_0]     14.461110 s: VHWA: VISS Init ... Done !!!
[MCU2_0]     14.461178 s: VHWA: VPAC Init ... Done !!!
[MCU2_0]     14.461222 s:  VX_ZONE_INIT:Enabled
[MCU2_0]     14.461252 s:  VX_ZONE_ERROR:Enabled
[MCU2_0]     14.461279 s:  VX_ZONE_WARNING:Enabled
[MCU2_0]     14.462983 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target MCU2-0 
[MCU2_0]     14.463249 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target VPAC_NF 
[MCU2_0]     14.463482 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target VPAC_LDC1 
[MCU2_0]     14.463719 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target VPAC_MSC1 
[MCU2_0]     14.464142 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target VPAC_MSC2 
[MCU2_0]     14.464432 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target VPAC_VISS1 
[MCU2_0]     14.464692 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target CAPTURE1 
[MCU2_0]     14.465090 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target CAPTURE2 
[MCU2_0]     14.465380 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target DISPLAY1 
[MCU2_0]     14.465661 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target DISPLAY2 
[MCU2_0]     14.466037 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target CSITX 
[MCU2_0]     14.466337 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target CAPTURE3 
[MCU2_0]     14.466610 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target CAPTURE4 
[MCU2_0]     14.467000 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target CAPTURE5 
[MCU2_0]     14.467298 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target CAPTURE6 
[MCU2_0]     14.467562 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target CAPTURE7 
[MCU2_0]     14.467930 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target CAPTURE8 
[MCU2_0]     14.468189 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target DSS_M2M1 
[MCU2_0]     14.468440 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target DSS_M2M2 
[MCU2_0]     14.468681 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target DSS_M2M3 
[MCU2_0]     14.469078 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target DSS_M2M4 
[MCU2_0]     14.469140 s:  VX_ZONE_INIT:[tivxInitLocal:130] Initialization Done !!!
[MCU2_0]     14.469175 s: APP: OpenVX Target kernel init ... !!!
[MCU2_0]     14.490284 s: APP: OpenVX Target kernel init ... Done !!!
[MCU2_0]     14.490350 s: CSI2RX: Init ... !!!
[MCU2_0]     14.490376 s: SCICLIENT: Sciclient_pmSetModuleState module=25 state=2
[MCU2_0]     14.490525 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]     14.490568 s: SCICLIENT: Sciclient_pmSetModuleState module=26 state=2
[MCU2_0]     14.490752 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]     14.490895 s: SCICLIENT: Sciclient_pmSetModuleState module=27 state=2
[MCU2_0]     14.491073 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]     14.491110 s: SCICLIENT: Sciclient_pmSetModuleState module=147 state=2
[MCU2_0]     14.491229 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]     14.491261 s: SCICLIENT: Sciclient_pmSetModuleState module=148 state=2
[MCU2_0]     14.491356 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]     14.491587 s: CSI2RX: Init ... Done !!!
[MCU2_0]     14.491626 s: CSI2TX: Init ... !!!
[MCU2_0]     14.491651 s: SCICLIENT: Sciclient_pmSetModuleState module=25 state=2
[MCU2_0]     14.491756 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]     14.491916 s: SCICLIENT: Sciclient_pmSetModuleState module=28 state=2
[MCU2_0]     14.492081 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]     14.492118 s: SCICLIENT: Sciclient_pmSetModuleState module=296 state=2
[MCU2_0]     14.492266 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]     14.492370 s: CSI2TX: Init ... Done !!!
[MCU2_0]     14.492407 s: ISS: Init ... !!!
[MCU2_0]     14.492446 s: IssSensor_Init ... Done !!!
[MCU2_0]     14.492529 s: IttRemoteServer_Init ... Done !!!
[MCU2_0]     14.492564 s: VISS REMOTE SERVICE: Init ... !!!
[MCU2_0]     14.492629 s: VISS REMOTE SERVICE: Init ... Done !!!
[MCU2_0]     14.492660 s: UDMA Copy: Init ... !!!
[MCU2_0]     14.495183 s: UDMA Copy: Init ... Done !!!
[MCU2_0]     14.495293 s: APP: Init ... Done !!!
[MCU2_0]     14.495327 s: APP: Run ... !!!
[MCU2_0]     14.495350 s: IPC: Starting echo test ...
[MCU2_0]     14.499230 s: APP: Run ... Done !!!
[MCU2_0]     14.501656 s: IPC: Echo status: mpu1_0[x] mcu2_0[s] mcu2_1[P] mcu3_0[.] mcu3_1[.] C66X_1[.] C66X_2[.] C7X_1[.] 
[MCU2_0]     14.501956 s: IPC: Echo status: mpu1_0[x] mcu2_0[s] mcu2_1[P] mcu3_0[P] mcu3_1[.] C66X_1[.] C66X_2[.] C7X_1[.] 
[MCU2_0]     14.502090 s: IPC: Echo status: mpu1_0[x] mcu2_0[s] mcu2_1[P] mcu3_0[P] mcu3_1[P] C66X_1[.] C66X_2[.] C7X_1[.] 
[MCU2_0]     14.502204 s: IPC: Echo status: mpu1_0[x] mcu2_0[s] mcu2_1[P] mcu3_0[P] mcu3_1[P] C66X_1[P] C66X_2[.] C7X_1[.] 
[MCU2_0]     14.502311 s: IPC: Echo status: mpu1_0[x] mcu2_0[s] mcu2_1[P] mcu3_0[P] mcu3_1[P] C66X_1[P] C66X_2[P] C7X_1[.] 
[MCU2_0]     14.502417 s: IPC: Echo status: mpu1_0[x] mcu2_0[s] mcu2_1[P] mcu3_0[P] mcu3_1[P] C66X_1[P] C66X_2[P] C7X_1[P] 
[MCU2_0]     14.536031 s: Function:CpswProxyServer_attachExtHandlerCb,HostId:0,CpswType:6
[MCU2_0]     15.535876 s: Assertion @ Line: 1212 in enet_mcm.c: false : failed !!!
[MCU2_0]     16.701821 s: Function:CpswProxyServer_registerMacHandlerCb,HostId:0,Handle:a3ac5f84,CoreKey:38acb7e6, MacAddress:70:ff:76:1d:92:c2, FlowIdx:173, FlowIdxOffset:1
[MCU2_0]     16.717434 s: Function:CpswProxyServer_setPromiscModeHandlerCb,HostId:0,Handle:a3ac5f84,CoreKey:38acb7e6,mode:disable
[MCU2_0]     16.717723 s: Function:CpswProxyServer_setPromiscModeHandlerCb,HostId:0,Handle:a3ac5f84,CoreKey:38acb7e6,mode:disable
[MCU2_0]     16.728167 s: Function:CpswProxyServer_setPromiscModeHandlerCb,HostId:0,Handle:a3ac5f84,CoreKey:38acb7e6,mode:disable
[MCU2_0]     16.739218 s: Function:CpswProxyServer_registerMacHandlerCb,HostId:0,Handle:a3ac5f84,CoreKey:38acb7e6, MacAddress:70:ff:76:1d:92:c1, FlowIdx:172, FlowIdxOffset:0
[MCU2_0]     16.742408 s: Cpsw_ioctlInternal: CPSW: Registered MAC address. ALE entry:7, Policer Entry:2
[MCU2_0]     16.750853 s: Function:CpswProxyServer_filterAddMacHandlerCb,HostId:0,Handle:a3ac5f84,CoreKey:38acb7e6, MacAddress:33:33:0:0:0:1, vlanId:0, FlowIdx:172, FlowIdOffset:0
[MCU2_0]     16.755208 s: Function:CpswProxyServer_filterAddMacHandlerCb,HostId:0,Handle:a3ac5f84,CoreKey:38acb7e6, MacAddress:1:0:5e:0:0:1, vlanId:0, FlowIdx:172, FlowIdOffset:0
[MCU2_0]     16.758849 s: Function:CpswProxyServer_filterAddMacHandlerCb,HostId:0,Handle:a3ac5f84,CoreKey:38acb7e6, MacAddress:33:33:ff:1d:92:c1, vlanId:0, FlowIdx:172, FlowIdOffset:0
[MCU2_0]     16.976708 s: Function:CpswProxyServer_setPromiscModeHandlerCb,HostId:0,Handle:a3ac5f84,CoreKey:38acb7e6,mode:disable
[MCU2_0]     16.977142 s: Function:CpswProxyServer_setPromiscModeHandlerCb,HostId:0,Handle:a3ac5f84,CoreKey:38acb7e6,mode:disable
[MCU2_0]     17.033403 s: Function:CpswProxyServer_filterAddMacHandlerCb,HostId:0,Handle:a3ac5f84,CoreKey:38acb7e6, MacAddress:1:80:c2:0:0:0, vlanId:0, FlowIdx:172, FlowIdOffset:0
[MCU2_0]     17.036878 s: Function:CpswProxyServer_filterAddMacHandlerCb,HostId:0,Handle:a3ac5f84,CoreKey:38acb7e6, MacAddress:1:80:c2:0:0:3, vlanId:0, FlowIdx:172, FlowIdOffset:0
[MCU2_0]     17.040307 s: Function:CpswProxyServer_filterAddMacHandlerCb,HostId:0,Handle:a3ac5f84,CoreKey:38acb7e6, MacAddress:1:80:c2:0:0:e, vlanId:0, FlowIdx:172, FlowIdOffset:0
[MCU2_0]     17.040457 s: CpswProxyServer_isRsvdMcast: Reserved mcast cannot be added to filter
[MCU2_0]     17.117712 s: Function:CpswProxyServer_setPromiscModeHandlerCb,HostId:0,Handle:a3ac5f84,CoreKey:38acb7e6,mode:disable
[MCU2_0]     17.117959 s: Function:CpswProxyServer_filterAddMacHandlerCb,HostId:0,Handle:a3ac5f84,CoreKey:38acb7e6, MacAddress:33:33:0:0:0:fb, vlanId:0, FlowIdx:172, FlowIdOffset:0
[MCU2_0]     18.013672 s: Function:CpswProxyServer_filterAddMacHandlerCb,HostId:0,Handle:a3ac5f84,CoreKey:38acb7e6, MacAddress:33:33:0:1:0:3, vlanId:0, FlowIdx:172, FlowIdOffset:0
[MCU2_0]     18.480823 s: Function:CpswProxyServer_setPromiscModeHandlerCb,HostId:0,Handle:a3ac5f84,CoreKey:38acb7e6,mode:disable
[MCU2_0]     20.273118 s: Function:CpswProxyServer_unregisterMacHandlerCb,HostId:0,Handle:a3ac5f84,CoreKey:38acb7e6, MacAddress:70:ff:76:1d:92:c1, FlowIdx:172, FlowIdOffset:0
[MCU2_0]     20.273593 s: Function:CpswProxyServer_filterDelMacHandlerCb,HostId:0,Handle:a3ac5f84,CoreKey:38acb7e6, MacAddress:33:33:0:0:0:1, vlanId:0, FlowIdx:172, FlowIdOffset:0
[MCU2_0]     20.274090 s: Function:CpswProxyServer_filterDelMacHandlerCb,HostId:0,Handle:a3ac5f84,CoreKey:38acb7e6, MacAddress:1:0:5e:0:0:1, vlanId:0, FlowIdx:172, FlowIdOffset:0
[MCU2_0]     20.274467 s: Function:CpswProxyServer_filterDelMacHandlerCb,HostId:0,Handle:a3ac5f84,CoreKey:38acb7e6, MacAddress:33:33:ff:1d:92:c1, vlanId:0, FlowIdx:172, FlowIdOffset:0
[MCU2_0]     20.274903 s: Function:CpswProxyServer_filterDelMacHandlerCb,HostId:0,Handle:a3ac5f84,CoreKey:38acb7e6, MacAddress:1:80:c2:0:0:0, vlanId:0, FlowIdx:172, FlowIdOffset:0
[MCU2_0]     20.275335 s: Function:CpswProxyServer_filterDelMacHandlerCb,HostId:0,Handle:a3ac5f84,CoreKey:38acb7e6, MacAddress:1:80:c2:0:0:3, vlanId:0, FlowIdx:172, FlowIdOffset:0
[MCU2_0]     20.275714 s: Function:CpswProxyServer_filterDelMacHandlerCb,HostId:0,Handle:a3ac5f84,CoreKey:38acb7e6, MacAddress:1:80:c2:0:0:e, vlanId:0, FlowIdx:172, FlowIdOffset:0
[MCU2_0]     20.275919 s: CpswProxyServer_isRsvdMcast: Reserved mcast cannot be added to filter
[MCU2_0]     20.276162 s: Function:CpswProxyServer_filterDelMacHandlerCb,HostId:0,Handle:a3ac5f84,CoreKey:38acb7e6, MacAddress:33:33:0:0:0:fb, vlanId:0, FlowIdx:172, FlowIdOffset:0
[MCU2_0]     20.276548 s: Function:CpswProxyServer_filterDelMacHandlerCb,HostId:0,Handle:a3ac5f84,CoreKey:38acb7e6, MacAddress:33:33:0:1:0:3, vlanId:0, FlowIdx:172, FlowIdOffset:0
[MCU2_0]     20.403643 s: Function:CpswProxyServer_setPromiscModeHandlerCb,HostId:0,Handle:a3ac5f84,CoreKey:38acb7e6,mode:disable
[MCU2_0]     20.403883 s: Function:CpswProxyServer_unregisterMacHandlerCb,HostId:0,Handle:a3ac5f84,CoreKey:38acb7e6, MacAddress:70:ff:76:1d:92:c2, FlowIdx:173, FlowIdOffset:1
[MCU2_0]     21.532485 s: Function:CpswProxyServer_registerIpv4MacHandlerCb,HostId:0,Handle:a3ac5f84,CoreKey:38acb7e6, MacAddress:70:ff:76:1d:92:c1 IPv4Addr:192.168.1.205
[MCU2_0]     21.532661 s: 
[MCU2_0]  SNo.      IP Address          MAC Address   
[MCU2_0]     21.532704 s: ------    -------------     -----------------
[MCU2_0]     21.532741 s:   1       192.168.1.205     70:ff:76:1d:92:c1
[MCU2_0]     21.533883 s: Function:CpswProxyServer_registerMacHandlerCb,HostId:0,Handle:a3ac5f84,CoreKey:38acb7e6, MacAddress:70:ff:76:1d:92:c1, FlowIdx:172, FlowIdxOffset:0
[MCU2_0]     21.537020 s: Cpsw_ioctlInternal: CPSW: Registered MAC address. ALE entry:6, Policer Entry:1
[MCU2_0]     21.552914 s: Function:CpswProxyServer_filterAddMacHandlerCb,HostId:0,Handle:a3ac5f84,CoreKey:38acb7e6, MacAddress:1:0:5e:0:0:1, vlanId:0, FlowIdx:172, FlowIdOffset:0
[MCU2_0]     21.556356 s: Function:CpswProxyServer_filterAddMacHandlerCb,HostId:0,Handle:a3ac5f84,CoreKey:38acb7e6, MacAddress:1:0:5e:0:0:fb, vlanId:0, FlowIdx:172, FlowIdOffset:0
[MCU2_0]     21.559843 s: Function:CpswProxyServer_filterAddMacHandlerCb,HostId:0,Handle:a3ac5f84,CoreKey:38acb7e6, MacAddress:1:80:c2:0:0:0, vlanId:0, FlowIdx:172, FlowIdOffset:0
[MCU2_0]     21.563113 s: Function:CpswProxyServer_registerMacHandlerCb,HostId:0,Handle:a3ac5f84,CoreKey:38acb7e6, MacAddress:70:ff:76:1d:92:c2, FlowIdx:173, FlowIdxOffset:1
[MCU2_0]     21.565055 s: Function:CpswProxyServer_filterAddMacHandlerCb,HostId:0,Handle:a3ac5f84,CoreKey:38acb7e6, MacAddress:1:80:c2:0:0:3, vlanId:0, FlowIdx:172, FlowIdOffset:0
[MCU2_0]     21.568569 s: CpswProxyServer_isRsvdMcast: Reserved mcast cannot be added to filter
[MCU2_1]      3.812888 s: CIO: Init ... Done !!!
[MCU2_1]      3.812961 s: ### CPU Frequency = 1000000000 Hz
[MCU2_1]      3.813004 s: CPU is running FreeRTOS
[MCU2_1]      3.813031 s: APP: Init ... !!!
[MCU2_1]      3.813055 s: SCICLIENT: Init ... !!!
[MCU2_1]      3.813334 s: SCICLIENT: DMSC FW version [8.6.3--v08.06.03 (Chill Capybar]
[MCU2_1]      3.813405 s: SCICLIENT: DMSC FW revision 0x8  
[MCU2_1]      3.813443 s: SCICLIENT: DMSC FW ABI revision 3.1
[MCU2_1]      3.813481 s: SCICLIENT: Init ... Done !!!
[MCU2_1]      3.813510 s: UDMA: Init ... !!!
[MCU2_1]      3.815575 s: UDMA: Init ... Done !!!
[MCU2_1]      3.815642 s: MEM: Init ... !!!
[MCU2_1]      3.815686 s: MEM: Created heap (DDR_LOCAL_MEM, id=0, flags=0x00000004) @ da000000 of size 16777216 bytes !!!
[MCU2_1]      3.815764 s: MEM: Created heap (L3_MEM, id=1, flags=0x00000001) @ 3640000 of size 262144 bytes !!!
[MCU2_1]      3.815825 s: MEM: Init ... Done !!!
[MCU2_1]      3.815851 s: IPC: Init ... !!!
[MCU2_1]      3.815915 s: IPC: 8 CPUs participating in IPC !!!
[MCU2_1]      3.815967 s: IPC: Waiting for HLOS to be ready ... !!!
[MCU2_1]     13.777722 s: IPC: HLOS is ready !!!
[MCU2_1]     13.798854 s: IPC: Init ... Done !!!
[MCU2_1]     13.798922 s: APP: Syncing with 7 CPUs ... !!!
[MCU2_1]     14.227414 s: APP: Syncing with 7 CPUs ... Done !!!
[MCU2_1]     14.227650 s: REMOTE_SERVICE: Init ... !!!
[MCU2_1]     14.229372 s: REMOTE_SERVICE: Init ... Done !!!
[MCU2_1]     14.229454 s: FVID2: Init ... !!!
[MCU2_1]     14.229525 s: FVID2: Init ... Done !!!
[MCU2_1]     14.229562 s: VHWA: DMPAC: Init ... !!!
[MCU2_1]     14.229589 s: SCICLIENT: Sciclient_pmSetModuleState module=48 state=2
[MCU2_1]     14.230145 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_1]     14.230189 s: SCICLIENT: Sciclient_pmSetModuleState module=305 state=2
[MCU2_1]     14.230724 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_1]     14.230765 s: VHWA: DOF Init ... !!!
[MCU2_1]     14.239835 s: VHWA: DOF Init ... Done !!!
[MCU2_1]     14.239903 s: VHWA: SDE Init ... !!!
[MCU2_1]     14.242706 s: VHWA: SDE Init ... Done !!!
[MCU2_1]     14.242766 s: VHWA: DMPAC: Init ... Done !!!
[MCU2_1]     14.242816 s:  VX_ZONE_INIT:Enabled
[MCU2_1]     14.242849 s:  VX_ZONE_ERROR:Enabled
[MCU2_1]     14.242875 s:  VX_ZONE_WARNING:Enabled
[MCU2_1]     14.244285 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target MCU2-1 
[MCU2_1]     14.244546 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target DMPAC_SDE 
[MCU2_1]     14.244775 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target DMPAC_DOF 
[MCU2_1]     14.244834 s:  VX_ZONE_INIT:[tivxInitLocal:130] Initialization Done !!!
[MCU2_1]     14.244872 s: APP: OpenVX Target kernel init ... !!!
[MCU2_1]     14.245155 s: APP: OpenVX Target kernel init ... Done !!!
[MCU2_1]     14.245199 s: UDMA Copy: Init ... !!!
[MCU2_1]     14.247074 s: UDMA Copy: Init ... Done !!!
[MCU2_1]     14.247145 s: APP: Init ... Done !!!
[MCU2_1]     14.247179 s: APP: Run ... !!!
[MCU2_1]     14.247205 s: IPC: Starting echo test ...
[MCU2_1]     14.250607 s: APP: Run ... Done !!!
[MCU2_1]     14.252234 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[s] mcu3_0[.] mcu3_1[.] C66X_1[P] C66X_2[.] C7X_1[.] 
[MCU2_1]     14.252361 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[s] mcu3_0[P] mcu3_1[.] C66X_1[P] C66X_2[.] C7X_1[.] 
[MCU2_1]     14.252487 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[s] mcu3_0[P] mcu3_1[P] C66X_1[P] C66X_2[.] C7X_1[.] 
[MCU2_1]     14.252592 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[s] mcu3_0[P] mcu3_1[P] C66X_1[P] C66X_2[P] C7X_1[.] 
[MCU2_1]     14.252696 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[s] mcu3_0[P] mcu3_1[P] C66X_1[P] C66X_2[P] C7X_1[P] 
[MCU2_1]     14.501578 s: IPC: Echo status: mpu1_0[x] mcu2_0[P] mcu2_1[s] mcu3_0[P] mcu3_1[P] C66X_1[P] C66X_2[P] C7X_1[P] 
[MCU3_0]      3.844181 s: CIO: Init ... Done !!!
[MCU3_0]      3.844246 s: ### CPU Frequency = 1000000000 Hz
[MCU3_0]      3.844288 s: CPU is running FreeRTOS
[MCU3_0]      3.844313 s: APP: Init ... !!!
[MCU3_0]      3.844336 s: SCICLIENT: Init ... !!!
[MCU3_0]      3.844613 s: SCICLIENT: DMSC FW version [8.6.3--v08.06.03 (Chill Capybar]
[MCU3_0]      3.844668 s: SCICLIENT: DMSC FW revision 0x8  
[MCU3_0]      3.844724 s: SCICLIENT: DMSC FW ABI revision 3.1
[MCU3_0]      3.844763 s: SCICLIENT: Init ... Done !!!
[MCU3_0]      3.844791 s: MEM: Init ... !!!
[MCU3_0]      3.844828 s: MEM: Created heap (DDR_LOCAL_MEM, id=0, flags=0x00000004) @ db000000 of size 8388608 bytes !!!
[MCU3_0]      3.844895 s: MEM: Init ... Done !!!
[MCU3_0]      3.844921 s: IPC: Init ... !!!
[MCU3_0]      3.844980 s: IPC: 8 CPUs participating in IPC !!!
[MCU3_0]      3.845033 s: IPC: Waiting for HLOS to be ready ... !!!
[MCU3_0]     14.081532 s: IPC: HLOS is ready !!!
[MCU3_0]     14.102894 s: IPC: Init ... Done !!!
[MCU3_0]     14.102961 s: APP: Syncing with 7 CPUs ... !!!
[MCU3_0]     14.227414 s: APP: Syncing with 7 CPUs ... Done !!!
[MCU3_0]     14.227469 s: REMOTE_SERVICE: Init ... !!!
[MCU3_0]     14.229523 s: REMOTE_SERVICE: Init ... Done !!!
[MCU3_0]     14.229599 s:  VX_ZONE_INIT:Enabled
[MCU3_0]     14.229630 s:  VX_ZONE_ERROR:Enabled
[MCU3_0]     14.229654 s:  VX_ZONE_WARNING:Enabled
[MCU3_0]     14.230963 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target MCU3-0 
[MCU3_0]     14.231029 s:  VX_ZONE_INIT:[tivxInitLocal:130] Initialization Done !!!
[MCU3_0]     14.231064 s: APP: OpenVX Target kernel init ... !!!
[MCU3_0]     14.231092 s: APP: OpenVX Target kernel init ... Done !!!
[MCU3_0]     14.231121 s: APP: Init ... Done !!!
[MCU3_0]     14.231146 s: APP: Run ... !!!
[MCU3_0]     14.231168 s: IPC: Starting echo test ...
[MCU3_0]     14.234576 s: APP: Run ... Done !!!
[MCU3_0]     14.236264 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[s] mcu3_1[.] C66X_1[.] C66X_2[.] C7X_1[P] 
[MCU3_0]     14.236387 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[s] mcu3_1[.] C66X_1[P] C66X_2[.] C7X_1[P] 
[MCU3_0]     14.236592 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[s] mcu3_1[.] C66X_1[P] C66X_2[P] C7X_1[P] 
[MCU3_0]     14.236847 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[s] mcu3_1[P] C66X_1[P] C66X_2[P] C7X_1[P] 
[MCU3_0]     14.251400 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[P] mcu3_0[s] mcu3_1[P] C66X_1[P] C66X_2[P] C7X_1[P] 
[MCU3_0]     14.501600 s: IPC: Echo status: mpu1_0[x] mcu2_0[P] mcu2_1[P] mcu3_0[s] mcu3_1[P] C66X_1[P] C66X_2[P] C7X_1[P] 
[MCU3_1]      3.877506 s: CIO: Init ... Done !!!
[MCU3_1]      3.877574 s: ### CPU Frequency = 1000000000 Hz
[MCU3_1]      3.877614 s: CPU is running FreeRTOS
[MCU3_1]      3.877639 s: APP: Init ... !!!
[MCU3_1]      3.877663 s: SCICLIENT: Init ... !!!
[MCU3_1]      3.877940 s: SCICLIENT: DMSC FW version [8.6.3--v08.06.03 (Chill Capybar]
[MCU3_1]      3.877990 s: SCICLIENT: DMSC FW revision 0x8  
[MCU3_1]      3.878039 s: SCICLIENT: DMSC FW ABI revision 3.1
[MCU3_1]      3.878079 s: SCICLIENT: Init ... Done !!!
[MCU3_1]      3.878107 s: MEM: Init ... !!!
[MCU3_1]      3.878145 s: MEM: Created heap (DDR_LOCAL_MEM, id=0, flags=0x00000004) @ db800000 of size 8388608 bytes !!!
[MCU3_1]      3.878210 s: MEM: Init ... Done !!!
[MCU3_1]      3.878235 s: IPC: Init ... !!!
[MCU3_1]      3.878296 s: IPC: 8 CPUs participating in IPC !!!
[MCU3_1]      3.878345 s: IPC: Waiting for HLOS to be ready ... !!!
[MCU3_1]     14.206104 s: IPC: HLOS is ready !!!
[MCU3_1]     14.227301 s: IPC: Init ... Done !!!
[MCU3_1]     14.227367 s: APP: Syncing with 7 CPUs ... !!!
[MCU3_1]     14.227415 s: APP: Syncing with 7 CPUs ... Done !!!
[MCU3_1]     14.227453 s: REMOTE_SERVICE: Init ... !!!
[MCU3_1]     14.229526 s: REMOTE_SERVICE: Init ... Done !!!
[MCU3_1]     14.229605 s:  VX_ZONE_INIT:Enabled
[MCU3_1]     14.229635 s:  VX_ZONE_ERROR:Enabled
[MCU3_1]     14.229664 s:  VX_ZONE_WARNING:Enabled
[MCU3_1]     14.230975 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target MCU3-1 
[MCU3_1]     14.231049 s:  VX_ZONE_INIT:[tivxInitLocal:130] Initialization Done !!!
[MCU3_1]     14.231088 s: APP: OpenVX Target kernel init ... !!!
[MCU3_1]     14.231118 s: APP: OpenVX Target kernel init ... Done !!!
[MCU3_1]     14.231149 s: APP: Init ... Done !!!
[MCU3_1]     14.231174 s: APP: Run ... !!!
[MCU3_1]     14.231198 s: IPC: Starting echo test ...
[MCU3_1]     14.234621 s: APP: Run ... Done !!!
[MCU3_1]     14.236329 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[.] mcu3_1[s] C66X_1[P] C66X_2[.] C7X_1[.] 
[MCU3_1]     14.236457 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[.] mcu3_1[s] C66X_1[P] C66X_2[.] C7X_1[P] 
[MCU3_1]     14.236660 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[s] C66X_1[P] C66X_2[.] C7X_1[P] 
[MCU3_1]     14.236839 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[s] C66X_1[P] C66X_2[P] C7X_1[P] 
[MCU3_1]     14.251413 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[P] mcu3_0[P] mcu3_1[s] C66X_1[P] C66X_2[P] C7X_1[P] 
[MCU3_1]     14.501618 s: IPC: Echo status: mpu1_0[x] mcu2_0[P] mcu2_1[P] mcu3_0[P] mcu3_1[s] C66X_1[P] C66X_2[P] C7X_1[P] 
[C6x_1 ]      3.919246 s: CIO: Init ... Done !!!
[C6x_1 ]      3.919273 s: ### CPU Frequency = 1350000000 Hz
[C6x_1 ]      3.919283 s: CPU is running FreeRTOS
[C6x_1 ]      3.919291 s: APP: Init ... !!!
[C6x_1 ]      3.919298 s: SCICLIENT: Init ... !!!
[C6x_1 ]      3.919545 s: SCICLIENT: DMSC FW version [8.6.3--v08.06.03 (Chill Capybar]
[C6x_1 ]      3.919556 s: SCICLIENT: DMSC FW revision 0x8  
[C6x_1 ]      3.919565 s: SCICLIENT: DMSC FW ABI revision 3.1
[C6x_1 ]      3.919575 s: SCICLIENT: Init ... Done !!!
[C6x_1 ]      3.919584 s: UDMA: Init ... !!!
[C6x_1 ]      3.921644 s: UDMA: Init ... Done !!!
[C6x_1 ]      3.921663 s: MEM: Init ... !!!
[C6x_1 ]      3.921676 s: MEM: Created heap (DDR_LOCAL_MEM, id=0, flags=0x00000004) @ dc000000 of size 16777216 bytes !!!
[C6x_1 ]      3.921693 s: MEM: Created heap (L2_MEM, id=2, flags=0x00000001) @ 800000 of size 229376 bytes !!!
[C6x_1 ]      3.921709 s: MEM: Created heap (DDR_SCRATCH_MEM, id=4, flags=0x00000001) @ dd000000 of size 50331648 bytes !!!
[C6x_1 ]      3.921725 s: MEM: Init ... Done !!!
[C6x_1 ]      3.921733 s: IPC: Init ... !!!
[C6x_1 ]      3.921754 s: IPC: 8 CPUs participating in IPC !!!
[C6x_1 ]      3.921767 s: IPC: Waiting for HLOS to be ready ... !!!
[C6x_1 ]     12.819947 s: IPC: HLOS is ready !!!
[C6x_1 ]     12.825245 s: IPC: Init ... Done !!!
[C6x_1 ]     12.825276 s: APP: Syncing with 7 CPUs ... !!!
[C6x_1 ]     14.227413 s: APP: Syncing with 7 CPUs ... Done !!!
[C6x_1 ]     14.227428 s: REMOTE_SERVICE: Init ... !!!
[C6x_1 ]     14.228157 s: REMOTE_SERVICE: Init ... Done !!!
[C6x_1 ]     14.228197 s:  VX_ZONE_INIT:Enabled
[C6x_1 ]     14.228208 s:  VX_ZONE_ERROR:Enabled
[C6x_1 ]     14.228219 s:  VX_ZONE_WARNING:Enabled
[C6x_1 ]     14.229122 s:  VX_ZONE_INIT:[tivxInitLocal:130] Initialization Done !!!
[C6x_1 ]     14.229137 s: APP: OpenVX Target kernel init ... !!!
[C6x_1 ]     14.229398 s: APP: OpenVX Target kernel init ... Done !!!
[C6x_1 ]     14.229415 s: UDMA Copy: Init ... !!!
[C6x_1 ]     14.233583 s: UDMA Copy: Init ... Done !!!
[C6x_1 ]     14.233604 s: APP: Init ... Done !!!
[C6x_1 ]     14.233613 s: APP: Run ... !!!
[C6x_1 ]     14.233621 s: IPC: Starting echo test ...
[C6x_1 ]     14.235125 s: APP: Run ... Done !!!
[C6x_1 ]     14.235530 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[.] mcu3_1[.] C66X_1[s] C66X_2[x] C7X_1[P] 
[C6x_1 ]     14.236012 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[.] mcu3_1[.] C66X_1[s] C66X_2[P] C7X_1[P] 
[C6x_1 ]     14.236073 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[.] C66X_1[s] C66X_2[P] C7X_1[P] 
[C6x_1 ]     14.236245 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[P] C66X_1[s] C66X_2[P] C7X_1[P] 
[C6x_1 ]     14.251269 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[P] mcu3_0[P] mcu3_1[P] C66X_1[s] C66X_2[P] C7X_1[P] 
[C6x_1 ]     14.501473 s: IPC: Echo status: mpu1_0[x] mcu2_0[P] mcu2_1[P] mcu3_0[P] mcu3_1[P] C66X_1[s] C66X_2[P] C7X_1[P] 
[C6x_2 ]      4.000063 s: CIO: Init ... Done !!!
[C6x_2 ]      4.000091 s: ### CPU Frequency = 1350000000 Hz
[C6x_2 ]      4.000101 s: CPU is running FreeRTOS
[C6x_2 ]      4.000109 s: APP: Init ... !!!
[C6x_2 ]      4.000117 s: SCICLIENT: Init ... !!!
[C6x_2 ]      4.000348 s: SCICLIENT: DMSC FW version [8.6.3--v08.06.03 (Chill Capybar]
[C6x_2 ]      4.000360 s: SCICLIENT: DMSC FW revision 0x8  
[C6x_2 ]      4.000369 s: SCICLIENT: DMSC FW ABI revision 3.1
[C6x_2 ]      4.000380 s: SCICLIENT: Init ... Done !!!
[C6x_2 ]      4.000389 s: UDMA: Init ... !!!
[C6x_2 ]      4.002460 s: UDMA: Init ... Done !!!
[C6x_2 ]      4.002480 s: MEM: Init ... !!!
[C6x_2 ]      4.002494 s: MEM: Created heap (DDR_LOCAL_MEM, id=0, flags=0x00000004) @ e0000000 of size 16777216 bytes !!!
[C6x_2 ]      4.002512 s: MEM: Created heap (L2_MEM, id=2, flags=0x00000001) @ 800000 of size 229376 bytes !!!
[C6x_2 ]      4.002527 s: MEM: Created heap (DDR_SCRATCH_MEM, id=4, flags=0x00000001) @ e1000000 of size 50331648 bytes !!!
[C6x_2 ]      4.002543 s: MEM: Init ... Done !!!
[C6x_2 ]      4.002552 s: IPC: Init ... !!!
[C6x_2 ]      4.002574 s: IPC: 8 CPUs participating in IPC !!!
[C6x_2 ]      4.002588 s: IPC: Waiting for HLOS to be ready ... !!!
[C6x_2 ]     12.985362 s: IPC: HLOS is ready !!!
[C6x_2 ]     12.990428 s: IPC: Init ... Done !!!
[C6x_2 ]     12.990455 s: APP: Syncing with 7 CPUs ... !!!
[C6x_2 ]     14.227413 s: APP: Syncing with 7 CPUs ... Done !!!
[C6x_2 ]     14.227428 s: REMOTE_SERVICE: Init ... !!!
[C6x_2 ]     14.228170 s: REMOTE_SERVICE: Init ... Done !!!
[C6x_2 ]     14.228208 s:  VX_ZONE_INIT:Enabled
[C6x_2 ]     14.228218 s:  VX_ZONE_ERROR:Enabled
[C6x_2 ]     14.228228 s:  VX_ZONE_WARNING:Enabled
[C6x_2 ]     14.229136 s:  VX_ZONE_INIT:[tivxInitLocal:130] Initialization Done !!!
[C6x_2 ]     14.229151 s: APP: OpenVX Target kernel init ... !!!
[C6x_2 ]     14.229414 s: APP: OpenVX Target kernel init ... Done !!!
[C6x_2 ]     14.229431 s: UDMA Copy: Init ... !!!
[C6x_2 ]     14.233970 s: UDMA Copy: Init ... Done !!!
[C6x_2 ]     14.233993 s: APP: Init ... Done !!!
[C6x_2 ]     14.234002 s: APP: Run ... !!!
[C6x_2 ]     14.234012 s: IPC: Starting echo test ...
[C6x_2 ]     14.235592 s: APP: Run ... Done !!!
[C6x_2 ]     14.236026 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[.] mcu3_1[.] C66X_1[P] C66X_2[s] C7X_1[.] 
[C6x_2 ]     14.236066 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[.] mcu3_1[.] C66X_1[P] C66X_2[s] C7X_1[P] 
[C6x_2 ]     14.236187 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[.] C66X_1[P] C66X_2[s] C7X_1[P] 
[C6x_2 ]     14.236268 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[P] C66X_1[P] C66X_2[s] C7X_1[P] 
[C6x_2 ]     14.251306 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[P] mcu3_0[P] mcu3_1[P] C66X_1[P] C66X_2[s] C7X_1[P] 
[C6x_2 ]     14.501501 s: IPC: Echo status: mpu1_0[x] mcu2_0[P] mcu2_1[P] mcu3_0[P] mcu3_1[P] C66X_1[P] C66X_2[s] C7X_1[P] 
[C7x_1 ]      4.222913 s: CIO: Init ... Done !!!
[C7x_1 ]      4.222927 s: ### CPU Frequency = 1000000000 Hz
[C7x_1 ]      4.222938 s: CPU is running FreeRTOS
[C7x_1 ]      4.222946 s: APP: Init ... !!!
[C7x_1 ]      4.222954 s: SCICLIENT: Init ... !!!
[C7x_1 ]      4.223200 s: SCICLIENT: DMSC FW version [8.6.3--v08.06.03 (Chill Capybar]
[C7x_1 ]      4.223214 s: SCICLIENT: DMSC FW revision 0x8  
[C7x_1 ]      4.223224 s: SCICLIENT: DMSC FW ABI revision 3.1
[C7x_1 ]      4.223235 s: SCICLIENT: Init ... Done !!!
[C7x_1 ]      4.223243 s: UDMA: Init ... !!!
[C7x_1 ]      4.224893 s: UDMA: Init ... Done !!!
[C7x_1 ]      4.224906 s: MEM: Init ... !!!
[C7x_1 ]      4.224917 s: MEM: Created heap (DDR_LOCAL_MEM, id=0, flags=0x00000004) @ 117000000 of size 268435456 bytes !!!
[C7x_1 ]      4.224936 s: MEM: Created heap (L3_MEM, id=1, flags=0x00000001) @ 70020000 of size 8159232 bytes !!!
[C7x_1 ]      4.224954 s: MEM: Created heap (L2_MEM, id=2, flags=0x00000001) @ 64800000 of size 458752 bytes !!!
[C7x_1 ]      4.224971 s: MEM: Created heap (L1_MEM, id=3, flags=0x00000001) @ 64e00000 of size 16384 bytes !!!
[C7x_1 ]      4.224987 s: MEM: Created heap (DDR_SCRATCH_MEM, id=4, flags=0x00000001) @ 100000000 of size 385875968 bytes !!!
[C7x_1 ]      4.225006 s: MEM: Init ... Done !!!
[C7x_1 ]      4.225014 s: IPC: Init ... !!!
[C7x_1 ]      4.225028 s: IPC: 8 CPUs participating in IPC !!!
[C7x_1 ]      4.225041 s: IPC: Waiting for HLOS to be ready ... !!!
[C7x_1 ]     13.475689 s: IPC: HLOS is ready !!!
[C7x_1 ]     13.478044 s: IPC: Init ... Done !!!
[C7x_1 ]     13.478059 s: APP: Syncing with 7 CPUs ... !!!
[C7x_1 ]     14.227415 s: APP: Syncing with 7 CPUs ... Done !!!
[C7x_1 ]     14.227432 s: REMOTE_SERVICE: Init ... !!!
[C7x_1 ]     14.227598 s: REMOTE_SERVICE: Init ... Done !!!
[C7x_1 ]     14.227619 s:  VX_ZONE_INIT:Enabled
[C7x_1 ]     14.227631 s:  VX_ZONE_ERROR:Enabled
[C7x_1 ]     14.227641 s:  VX_ZONE_WARNING:Enabled
[C7x_1 ]     14.227812 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-1 
[C7x_1 ]     14.227880 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-1_PRI_2 
[C7x_1 ]     14.227985 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-1_PRI_3 
[C7x_1 ]     14.228084 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-1_PRI_4 
[C7x_1 ]     14.228202 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-1_PRI_5 
[C7x_1 ]     14.228288 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-1_PRI_6 
[C7x_1 ]     14.228399 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-1_PRI_7 
[C7x_1 ]     14.228475 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-1_PRI_8 
[C7x_1 ]     14.228497 s:  VX_ZONE_INIT:[tivxInitLocal:130] Initialization Done !!!
[C7x_1 ]     14.228510 s: APP: OpenVX Target kernel init ... !!!
[C7x_1 ]     14.228654 s: APP: OpenVX Target kernel init ... Done !!!
[C7x_1 ]     14.228669 s: APP: Init ... Done !!!
[C7x_1 ]     14.228679 s: APP: Run ... !!!
[C7x_1 ]     14.228687 s: IPC: Starting echo test ...
[C7x_1 ]     14.228939 s: APP: Run ... Done !!!
[C7x_1 ]     14.235544 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[.] mcu3_1[.] C66X_1[P] C66X_2[x] C7X_1[s] 
[C7x_1 ]     14.236010 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[.] C66X_1[P] C66X_2[.] C7X_1[s] 
[C7x_1 ]     14.236051 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[.] C66X_1[P] C66X_2[P] C7X_1[s] 
[C7x_1 ]     14.236113 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[P] C66X_1[P] C66X_2[P] C7X_1[s] 
[C7x_1 ]     14.251334 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[P] mcu3_0[P] mcu3_1[P] C66X_1[P] C66X_2[P] C7X_1[s] 
[C7x_1 ]     14.501594 s: IPC: Echo status: mpu1_0[x] mcu2_0[P] mcu2_1[P] mcu3_0[P] mcu3_1[P] C66X_1[P] C66X_2[P] C7X_1[s] 

Best Regards,

Zhang

HI,Sudheer

      Thanks for your support.  When we patch patchs, we found some errors. The log as follows:

wx@wx-virtual-machine:~/ccuProject/ti_rtos_watt/pdk_jacinto_08_06_00_31/packages/ti/drv/enet$ patch -p1 < enet_mcm_race_condition_fix.patch 
patching file examples/enet_lwip_example/main.c
patching file examples/timesync/hal/src/timeSync_cpsw.c
patching file examples/timesync/hal/src/timeSync_icssg.c
patching file examples/utils/enet_mcm.c
Hunk #3 succeeded at 205 (offset 71 lines).
Hunk #4 succeeded at 225 (offset 71 lines).
Hunk #5 succeeded at 246 with fuzz 2 (offset 71 lines).
Hunk #6 FAILED at 218.
Hunk #7 FAILED at 262.
Hunk #8 succeeded at 268 (offset -10 lines).
Hunk #9 succeeded at 287 (offset -10 lines).
Hunk #10 succeeded at 304 (offset -10 lines).
Hunk #11 succeeded at 322 (offset -10 lines).
Hunk #12 succeeded at 340 (offset -10 lines).
Hunk #14 FAILED at 506.
3 out of 27 hunks FAILED -- saving rejects to file examples/utils/enet_mcm.c.rej
patching file examples/utils/include/enet_mcm.h

    We think this is a difference in version. The PDK we used: 08_06_00_31.

    Could you provide a patch base on pdk08_06_00_31?

Best Regards,

Zhang

Hi, 

Have you made any changes on top of TI SDK. If so, patch may not apply as is. 

Can you please look into patch files and integrate changes into your SDK, instead of applying the patches. 

Best Regards, 

Sudheer

HI,Sudheer

     Thanks for your support.

     We have tried to integrate changes into SDK base on patchs, but there are also some errors. And we found patch not base on  pdk08_06_00_31, so there are some difference. struct EnetMcm_Obj_s on pdk08_06_00_31 as follows:

typedef struct EnetMcm_Obj_s
{
    bool isInitDone;

    uint8_t refCnt;

    Enet_Type enetType;

    uint32_t instId;

    Enet_Handle hEnet;

    Udma_DrvHandle hUdmaDrv;

    Cpsw_Cfg cpswCfg;

#if defined(ENET_ENABLE_ICSSG)
    Icssg_Cfg icssgCfg;
#endif

    EnetUdma_Cfg dmaCfg;

    uint32_t selfCoreId;

    EnetMcm_setPortLinkCfg setPortLinkCfg;

    Enet_MacPort macPortList[ENET_MAC_PORT_NUM];

    uint8_t numMacPorts;

    TaskP_Handle task;

    MailboxP_Handle hMboxCmd;

    EnetMcm_RespMboxObj *hInternalClientRespMbox;

    QueueP_Handle hMboxRespFreeQ;

    EnetMcm_RespMboxObj respMbox[(ENETMCM_MAX_CLIENTS + 1)];

    ClockP_Handle hTimer;

    TaskP_Handle task_periodicTick;

    SemaphoreP_Handle timerSem;

    volatile bool timerTaskShutDownFlag;

    MutexP_Object mutexObj;

    MutexP_Handle hMutex;

    uint32_t periodicTaskPeriod;

    EnetMcm_CoreAttachTable coreAttachTable;

    Enet_Print print;

    /* Async IOCTL handling */

    /*! Whether an ICSSG async IOCTL is complete or not */
    volatile bool asyncIoctlDone;

    /*! Flag to indicate that async IOCTL task should be shut down */
    bool asyncIoctlTaskShutdown;

    /*! Async IOCTL task that pends on asyncIoctlSem and then indicates
     *  IOCTL completion */
    TaskP_Handle asyncIoctlTask;

    /*! Semaphore used to wait for async IOCTL completion. It's posted from
     *  async IOCTL callback which is called from Enet_poll() */
    SemaphoreP_Handle asyncIoctlSem;
}EnetMcm_Obj;

     there is no mcmResponseMbxBuf, so we think patch not base 08_06_00_31.

@@ -236,7 +266,7 @@ typedef struct EnetMcm_Obj_s                                                                    
     uint8_t mcmRequestMbxBuf[ENETMCM_MBOX_SIZE] __attribute__ ((aligned(32)));
 
-    uint8_t mcmResponseMbxBuf[ENETMCM_MBOX_SIZE] __attribute__ ((aligned(32)));
+    uint8_t mcmResponseMbxBuf[(ENETMCM_MAX_CLIENTS + 1)][ENETMCM_MBOX_SIZE] __attribute__ ((aligned(32)));
 }EnetMcm_Obj;

    Could you  comfirm on it?

Best Regards,

Zhang

Hi Zhang, 

The patch I have shared is which development team integrates into local repo. 

Let me check internally and gat back to you soon. 

Best Regards, 

Sudheer

Hi,Sudheer

     Thanks for your support.  we have patched this patches. And we found new problem, the log as follows:

     1.keeping  link down and no common caps found

[MCU2_0]    229.453939 s: Cpsw_handleLinkUp: Port 3: Link up: 1-Gbps Full-Duplex
[MCU2_0]    247.753650 s: Cpsw_handleLinkDown: Port 3: Link down
[MCU2_0]    251.553668 s: Cpsw_handleLinkUp: Port 3: Link up: 1-Gbps Full-Duplex
[MCU2_0]    286.253662 s: Cpsw_handleLinkDown: Port 3: Link down
[MCU2_0]    289.953940 s: Cpsw_handleLinkUp: Port 3: Link up: 1-Gbps Full-Duplex
[MCU2_0]    369.753653 s: Cpsw_handleLinkDown: Port 3: Link down
[MCU2_0]    373.453929 s: Cpsw_handleLinkUp: Port 3: Link up: 1-Gbps Full-Duplex
[MCU2_0]    375.253664 s: Cpsw_handleLinkDown: Port 3: Link down
[MCU2_0]    378.953937 s: Cpsw_handleLinkUp: Port 3: Link up: 1-Gbps Full-Duplex
[MCU2_0]    448.553647 s: Cpsw_handleLinkDown: Port 3: Link down
[MCU2_0]    452.353670 s: Cpsw_handleLinkUp: Port 3: Link up: 1-Gbps Full-Duplex
[MCU2_0]    473.453717 s: Cpsw_handleLinkDown: Port 3: Link down
[MCU2_0]    481.858895 s: Cpsw_handleLinkUp: Port 3: Link up: 1-Gbps Full-Duplex
[MCU2_0]    483.653649 s: Cpsw_handleLinkDown: Port 3: Link down
[MCU2_0]    487.353939 s: Cpsw_handleLinkUp: Port 3: Link up: 1-Gbps Full-Duplex
[MCU2_0]    489.953645 s: Cpsw_handleLinkDown: Port 3: Link down
[MCU2_0]    501.753908 s: EnetPhy_findCommonNwayCaps: PHY 0: no common caps found
[MCU2_0]    501.853938 s: Cpsw_handleLinkUp: Port 3: Link up: 1-Gbps Full-Duplex
[MCU2_0]    514.753652 s: Cpsw_handleLinkDown: Port 3: Link down
[MCU2_0]    518.453941 s: Cpsw_handleLinkUp: Port 3: Link up: 1-Gbps Full-Duplex
[MCU2_0]    521.253656 s: Cpsw_handleLinkDown: Port 3: Link down
[MCU2_0]    524.953936 s: Cpsw_handleLinkUp: Port 3: Link up: 1-Gbps Full-Duplex
[MCU2_0]    529.453650 s: Cpsw_handleLinkDown: Port 3: Link down
[MCU2_0]    533.153939 s: Cpsw_handleLinkUp: Port 3: Link up: 1-Gbps Full-Duplex
[MCU2_0]    536.553645 s: Cpsw_handleLinkDown: Port 3: Link down
[MCU2_0]    540.253934 s: Cpsw_handleLinkUp: Port 3: Link up: 1-Gbps Full-Duplex

    2.failed to read PHY Reg

[MCU2_0]   1140.214510 s: Mdio_ioctlManualMode: failed to read PHY 12 C22 reg 31: -1
[MCU2_0]   1140.214594 s: EnetPhyMdioDflt_readC22: PHY 12: Failed to read C22 reg: -1
[MCU2_0]   1140.214656 s: EnetPhy_readReg: PHY 12: Failed to read reg 31: -1
[MCU2_0]   1140.214872 s: Mdio_ioctlManualMode: failed to read PHY 0 C22 reg 31: -1
[MCU2_0]   1140.214936 s: EnetPhyMdioDflt_readC22: PHY 0: Failed to read C22 reg: -1
[MCU2_0]   1140.214997 s: EnetPhy_readReg: PHY 0: Failed to read reg 31: -1
[MCU2_0]   1140.215277 s: Mdio_ioctlManualMode: failed to read PHY 3 C22 reg 31: -1
[MCU2_0]   1140.215350 s: EnetPhyMdioDflt_readC22: PHY 3: Failed to read C22 reg: -1
[MCU2_0]   1140.215410 s: EnetPhy_readReg: PHY 3: Failed to read reg 31: -1
[MCU2_0]   1140.314297 s: Mdio_ioctlManualMode: failed to read PHY 12 C22 reg 31: -1
[MCU2_0]   1140.314393 s: EnetPhyMdioDflt_readC22: PHY 12: Failed to read C22 reg: -1
[MCU2_0]   1140.314715 s: EnetPhy_readReg: PHY 12: Failed to read reg 31: -1
[MCU2_0]   1140.314963 s: Mdio_ioctlManualMode: failed to read PHY 0 C22 reg 31: -1
[MCU2_0]   1140.315030 s: EnetPhyMdioDflt_readC22: PHY 0: Failed to read C22 reg: -1
[MCU2_0]   1140.315251 s: EnetPhy_readReg: PHY 0: Failed to read reg 31: -1
[MCU2_0]   1140.315408 s: Mdio_ioctlManualMode: failed to read PHY 3 C22 reg 31: -1
[MCU2_0]   1140.315470 s: EnetPhyMdioDflt_readC22: PHY 3: Failed to read C22 reg: -1
[MCU2_0]   1140.315525 s: EnetPhy_readReg: PHY 3: Failed to read reg 31: -1
[MCU2_0]   1140.514294 s: Mdio_ioctlManualMode: failed to read PHY 12 C22 reg 31: -1
[MCU2_0]   1140.514381 s: EnetPhyMdioDflt_readC22: PHY 12: Failed to read C22 reg: -1
[MCU2_0]   1140.614293 s: Mdio_ioctlManualMode: failed to read PHY 12 C22 reg 31: -1
[MCU2_0]   1140.614629 s: EnetPhyMdioDflt_readC22: PHY 12: Failed to read C22 reg: -1
[MCU2_0]   1140.614738 s: EnetPhy_readReg: PHY 12: Failed to read reg 31: -1
[MCU2_0]   1140.614972 s: Mdio_ioctlManualMode: failed to read PHY 0 C22 reg 31: -1
[MCU2_0]   1140.615037 s: EnetPhyMdioDflt_readC22: PHY 0: Failed to read C22 reg: -1
[MCU2_0]   1140.615248 s: EnetPhy_readReg: PHY 0: Failed to read reg 31: -1
[MCU2_0]   1140.615395 s: Mdio_ioctlManualMode: failed to read PHY 3 C22 reg 31: -1
[MCU2_0]   1140.615458 s: EnetPhyMdioDflt_readC22: PHY 3: Failed to read C22 reg: -1
[MCU2_0]   1140.615520 s: EnetPhy_readReg: PHY 3: Failed to read reg 31: -1
[MCU2_0]   1140.714287 s: Mdio_ioctlManualMode: failed to read PHY 12 C22 reg 31: -1
[MCU2_0]   1140.714380 s: EnetPhyMdioDflt_readC22: PHY 12: Failed to read C22 reg: -1
[MCU2_0]   1140.714711 s: EnetPhy_readReg: PHY 12: Failed to read reg 31: -1
[MCU2_0]   1140.714947 s: Mdio_ioctlManualMode: failed to read PHY 0 C22 reg 31: -1
[MCU2_0]   1140.715011 s: EnetPhyMdioDflt_readC22: PHY 0: Failed to read C22 reg: -1
[MCU2_0]   1140.715215 s: EnetPhy_readReg: PHY 0: Failed to read reg 31: -1
[MCU2_0]   1140.715373 s: Mdio_ioctlManualMode: failed to read PHY 3 C22 reg 31: -1
[MCU2_0]   1140.715434 s: EnetPhyMdioDflt_readC22: PHY 3: Failed to read C22 reg: -1
[MCU2_0]   1140.715594 s: EnetPhy_readReg: PHY 3: Failed to read reg 31: -1
[MCU2_0]   1140.814546 s: Mdio_ioctlManualMode: failed to read PHY 12 C22 reg 31: -1
[MCU2_0]   1140.814637 s: EnetPhyMdioDflt_readC22: PHY 12: Failed to read C22 reg: -1
[MCU2_0]   1140.814702 s: EnetPhy_readReg: PHY 12: Failed to read reg 31: -1
[MCU2_0]   1140.814927 s: Mdio_ioctlManualMode: failed to read PHY 0 C22 reg 31: -1
[MCU2_0]   1140.814987 s: EnetPhyMdioDflt_readC22: PHY 0: Failed to read C22 reg: -1
[MCU2_0]   1140.815254 s: EnetPhy_readReg: PHY 0: Failed to read reg 31: -1
[MCU2_0]   1140.815425 s: Mdio_ioctlManualMode: failed to read PHY 3 C22 reg 31: -1
[MCU2_0]   1140.815490 s: EnetPhyMdioDflt_readC22: PHY 3: Failed to read C22 reg: -1
[MCU2_0]   1140.815551 s: EnetPhy_readReg: PHY 3: Failed to read reg 31: -1
[MCU2_0]   1140.914295 s: Mdio_ioctlManualMode: failed to read PHY 12 C22 reg 31: -1
[MCU2_0]   1140.914385 s: EnetPhyMdioDflt_readC22: PHY 12: Failed to read C22 reg: -1
[MCU2_0]   1140.914719 s: EnetPhy_rmwReg: PHY 12: Failed to read reg 31: -1
[MCU2_0]   1140.914970 s: Mdio_ioctlManualMode: failed to read PHY 0 C22 reg 31: -1
[MCU2_0]   1140.915180 s: EnetPhyMdioDflt_readC22: PHY 0: Failed to read C22 reg: -1
[MCU2_0]   1140.915266 s: EnetPhy_readReg: PHY 0: Failed to read reg 31: -1
[MCU2_0]   1140.915425 s: Mdio_ioctlManualMode: failed to read PHY 3 C22 reg 31: -1
[MCU2_0]   1140.915489 s: EnetPhyMdioDflt_readC22: PHY 3: Failed to read C22 reg: -1
[MCU2_0]   1140.915545 s: EnetPhy_readReg: PHY 3: Failed to read reg 31: -1
[MCU2_0]   1141.014298 s: Mdio_ioctlManualMode: failed to read PHY 12 C22 reg 31: -1
[MCU2_0]   1141.014394 s: EnetPhyMdioDflt_readC22: PHY 12: Failed to read C22 reg: -1
[MCU2_0]   1141.014736 s: EnetPhy_readReg: PHY 12: Failed to read reg 31: -1
[MCU2_0]   1141.014964 s: Mdio_ioctlManualMode: failed to read PHY 0 C22 reg 31: -1
[MCU2_0]   1141.015025 s: EnetPhyMdioDflt_readC22: PHY 0: Failed to read C22 reg: -1
[MCU2_0]   1141.015228 s: EnetPhy_rmwReg: PHY 0: Failed to read reg 31: -1
[MCU2_0]   1141.015383 s: Mdio_ioctlManualMode: failed to read PHY 3 C22 reg 31: -1
[MCU2_0]   1141.015444 s: EnetPhyMdioDflt_readC22: PHY 3: Failed to read C22 reg: -1
[MCU2_0]   1141.015501 s: EnetPhy_readReg: PHY 3: Failed to read reg 31: -1
[MCU2_0]   1141.214613 s: EnetPhyMdioDflt_readC22: PHY 12: Failed to read C22 reg: -1
[MCU2_0]   1141.214677 s: EnetPhy_readReg: PHY 12: Failed to read reg 31: -1
[MCU2_0]   1141.214903 s: Mdio_ioctlManualMode: failed to read PHY 0 C22 reg 31: -1
[MCU2_0]   1141.214968 s: EnetPhyMdioDflt_readC22: PHY 0: Failed to read C22 reg: -1
[MCU2_0]   1141.215031 s: EnetPhy_readReg: PHY 0: Failed to read reg 31: -1
[MCU2_0]   1141.215325 s: Mdio_ioctlManualMode: failed to read PHY 3 C22 reg 31: -1
[MCU2_0]   1141.215385 s: EnetPhyMdioDflt_readC22: PHY 3: Failed to read C22 reg: -1
[MCU2_0]   1141.215443 s: EnetPhy_readReg: PHY 3: Failed to read reg 31: -1
[MCU2_0]   1141.315009 s: EnetPhyMdioDflt_readC22: PHY 0: Failed to read C22 reg: -1
[MCU2_0]   1141.315221 s: EnetPhy_readReg: PHY 0: Failed to read reg 31: -1
[MCU2_0]   1141.315384 s: Mdio_ioctlManualMode: failed to read PHY 3 C22 reg 31: -1
[MCU2_0]   1141.315444 s: EnetPhyMdioDflt_readC22: PHY 3: Failed to read C22 reg: -1
[MCU2_0]   1141.315498 s: EnetPhy_readReg: PHY 3: Failed to read reg 31: -1
[MCU2_0]   1141.514303 s: Mdio_ioctlManualMode: failed to read PHY 12 C22 reg 31: -1
[MCU2_0]   1141.514396 s: EnetPhyMdioDflt_readC22: PHY 12: Failed to read C22 reg: -1
[MCU2_0]   1141.514460 s: EnetPhy_readReg: PHY 12: Failed to read reg 31: -1
[MCU2_0]   1141.514975 s: Mdio_ioctlManualMode: failed to read PHY 0 C22 reg 31: -1
[MCU2_0]   1141.515181 s: EnetPhyMdioDflt_readC22: PHY 0: Failed to read C22 reg: -1
[MCU2_0]   1141.515261 s: EnetPhy_readReg: PHY 0: Failed to read reg 31: -1
[MCU2_0]   1141.515412 s: Mdio_ioctlManualMode: failed to read PHY 3 C22 reg 31: -1
[MCU2_0]   1141.515472 s: EnetPhyMdioDflt_readC22: PHY 3: Failed to read C22 reg: -1
[MCU2_0]   1141.515530 s: EnetPhy_readReg: PHY 3: Failed to read reg 31: -1
[MCU2_0]   1141.814296 s: Mdio_ioctlManualMode: failed to read PHY 12 C22 reg 31: -1
[MCU2_0]   1141.814392 s: EnetPhyMdioDflt_readC22: PHY 12: Failed to read C22 reg: -1
[MCU2_0]   1141.814459 s: EnetPhy_readReg: PHY 12: Failed to read reg 31: -1
[MCU2_0]   1141.814953 s: Mdio_ioctlManualMode: failed to read PHY 0 C22 reg 31: -1
[MCU2_0]   1141.815033 s: EnetPhyMdioDflt_readC22: PHY 0: Failed to read C22 reg: -1
[MCU2_0]   1141.815244 s: EnetPhy_readReg: PHY 0: Failed to read reg 31: -1
[MCU2_0]   1141.815395 s: Mdio_ioctlManualMode: failed to read PHY 3 C22 reg 31: -1
[MCU2_0]   1141.815453 s: EnetPhyMdioDflt_readC22: PHY 3: Failed to read C22 reg: -1
[MCU2_0]   1141.815507 s: EnetPhy_readReg: PHY 3: Failed to read reg 31: -1
[MCU2_0]   1141.914417 s: Mdio_ioctlManualMode: failed to read PHY 12 C22 reg 31: -1
[MCU2_0]   1141.914503 s: EnetPhyMdioDflt_readC22: PHY 12: Failed to read C22 reg: -1
[MCU2_0]   1141.914569 s: EnetPhy_readReg: PHY 12: Failed to read reg 31: -1
[MCU2_0]   1141.914787 s: Mdio_ioctlManualMode: failed to read PHY 0 C22 reg 31: -1
[MCU2_0]   1141.914852 s: EnetPhyMdioDflt_readC22: PHY 0: Failed to read C22 reg: -1
[MCU2_0]   1141.914911 s: EnetPhy_readReg: PHY 0: Failed to read reg 31: -1
[MCU2_0]   1141.915180 s: Mdio_ioctlManualMode: failed to read PHY 3 C22 reg 31: -1
[MCU2_0]   1141.915257 s: EnetPhyMdioDflt_readC22: PHY 3: Failed to read C22 reg: -1
[MCU2_0]   1141.915317 s: EnetPhy_readReg: PHY 3: Failed to read reg 31: -1
[MCU2_0]   1142.114291 s: Mdio_ioctlManualMode: failed to read PHY 12 C22 reg 31: -1
[MCU2_0]   1142.114387 s: EnetPhyMdioDflt_readC22: PHY 12: Failed to read C22 reg: -1
[MCU2_0]   1142.114734 s: EnetPhy_rmwReg: PHY 12: Failed to read reg 31: -1
[MCU2_0]   1142.114986 s: Mdio_ioctlManualMode: failed to read PHY 0 C22 reg 31: -1
[MCU2_0]   1142.214302 s: Mdio_ioctlManualMode: failed to read PHY 12 C22 reg 31: -1
[MCU2_0]   1142.214636 s: EnetPhyMdioDflt_readC22: PHY 12: Failed to read C22 reg: -1
[MCU2_0]   1142.214701 s: EnetPhy_readReg: PHY 12: Failed to read reg 31: -1
[MCU2_0]   1142.214932 s: Mdio_ioctlManualMode: failed to read PHY 0 C22 reg 31: -1
[MCU2_0]   1142.214993 s: EnetPhyMdioDflt_readC22: PHY 0: Failed to read C22 reg: -1
[MCU2_0]   1142.215200 s: EnetPhy_rmwReg: PHY 0: Failed to read reg 31: -1
[MCU2_0]   1142.215368 s: Mdio_ioctlManualMode: failed to read PHY 3 C22 reg 31: -1
[MCU2_0]   1142.215430 s: EnetPhyMdioDflt_readC22: PHY 3: Failed to read C22 reg: -1
[MCU2_0]   1142.215485 s: EnetPhy_readReg: PHY 3: Failed to read reg 31: -1
[MCU2_0]   1142.314300 s: Mdio_ioctlManualMode: failed to read PHY 12 C22 reg 31: -1
[MCU2_0]   1142.314659 s: EnetPhyMdioDflt_readC22: PHY 12: Failed to read C22 reg: -1
[MCU2_0]   1142.314741 s: EnetPhy_readReg: PHY 12: Failed to read reg 31: -1
[MCU2_0]   1142.314971 s: Mdio_ioctlManualMode: failed to read PHY 0 C22 reg 31: -1
[MCU2_0]   1142.315036 s: EnetPhyMdioDflt_readC22: PHY 0: Failed to read C22 reg: -1
[MCU2_0]   1142.315256 s: EnetPhy_readReg: PHY 0: Failed to read reg 31: -1
[MCU2_0]   1142.315409 s: Mdio_ioctlManualMode: failed to read PHY 3 C22 reg 31: -1
[MCU2_0]   1142.315469 s: EnetPhyMdioDflt_readC22: PHY 3: Failed to read C22 reg: -1
[MCU2_0]   1142.315527 s: EnetPhy_rmwReg: PHY 3: Failed to read reg 31: -1
[MCU2_0]   1142.414441 s: Mdio_ioctlManualMode: failed to read PHY 12 C22 reg 31: -1
[MCU2_0]   1142.414525 s: EnetPhyMdioDflt_readC22: PHY 12: Failed to read C22 reg: -1
[MCU2_0]   1142.414590 s: EnetPhy_readReg: PHY 12: Failed to read reg 31: -1
[MCU2_0]   1142.414802 s: Mdio_ioctlManualMode: failed to read PHY 0 C22 reg 31: -1
[MCU2_0]   1142.414865 s: EnetPhyMdioDflt_readC22: PHY 0: Failed to read C22 reg: -1
[MCU2_0]   1142.414922 s: EnetPhy_readReg: PHY 0: Failed to read reg 31: -1
[MCU2_0]   1142.415186 s: Mdio_ioctlManualMode: failed to read PHY 3 C22 reg 31: -1
[MCU2_0]   1142.415264 s: EnetPhyMdioDflt_readC22: PHY 3: Failed to read C22 reg: -1
[MCU2_0]   1142.415325 s: EnetPhy_readReg: PHY 3: Failed to read reg 31: -1
[MCU2_0]   1142.914386 s: Mdio_ioctlManualMode: failed to read PHY 12 C22 reg 31: -1
[MCU2_0]   1142.914477 s: EnetPhyMdioDflt_readC22: PHY 12: Failed to read C22 reg: -1
[MCU2_0]   1142.914540 s: EnetPhy_readReg: PHY 12: Failed to read reg 31: -1
[MCU2_0]   1142.914761 s: Mdio_ioctlManualMode: failed to read PHY 0 C22 reg 31: -1
[MCU2_0]   1142.914827 s: EnetPhyMdioDflt_readC22: PHY 0: Failed to read C22 reg: -1
[MCU2_0]   1142.914888 s: EnetPhy_readReg: PHY 0: Failed to read reg 31: -1
[MCU2_0]   1143.014423 s: Mdio_ioctlManualMode: failed to read PHY 12 C22 reg 31: -1
[MCU2_0]   1143.014504 s: EnetPhyMdioDflt_readC22: PHY 12: Failed to read C22 reg: -1
[MCU2_0]   1143.014566 s: EnetPhy_readReg: PHY 12: Failed to read reg 31: -1
[MCU2_0]   1143.014784 s: Mdio_ioctlManualMode: failed to read PHY 0 C22 reg 31: -1
[MCU2_0]   1143.014846 s: EnetPhyMdioDflt_readC22: PHY 0: Failed to read C22 reg: -1
[MCU2_0]   1143.014902 s: EnetPhy_readReg: PHY 0: Failed to read reg 31: -1
[MCU2_0]   1143.015036 s: Mdio_ioctlManualMode: failed to read PHY 3 C22 reg 31: -1
[MCU2_0]   1143.015242 s: EnetPhyMdioDflt_readC22: PHY 3: Failed to read C22 reg: -1
[MCU2_0]   1143.015303 s: EnetPhy_readReg: PHY 3: Failed to read reg 31: -1
[MCU2_0]   1143.114345 s: Mdio_ioctlManualMode: failed to read PHY 12 C22 reg 31: -1
[MCU2_0]   1143.114429 s: EnetPhyMdioDflt_readC22: PHY 12: Failed to read C22 reg: -1
[MCU2_0]   1143.114492 s: EnetPhy_readReg: PHY 12: Failed to read reg 31: -1
[MCU2_0]   1143.114706 s: Mdio_ioctlManualMode: failed to read PHY 0 C22 reg 31: -1
[MCU2_0]   1143.114768 s: EnetPhyMdioDflt_readC22: PHY 0: Failed to read C22 reg: -1
[MCU2_0]   1143.114825 s: EnetPhy_readReg: PHY 0: Failed to read reg 31: -1
[MCU2_0]   1143.114960 s: Mdio_ioctlManualMode: failed to read PHY 3 C22 reg 31: -1
[MCU2_0]   1143.115020 s: EnetPhyMdioDflt_readC22: PHY 3: Failed to read C22 reg: -1
[MCU2_0]   1143.115217 s: EnetPhy_readReg: PHY 3: Failed to read reg 31: -1
[MCU2_0]   1143.214338 s: Mdio_ioctlManualMode: failed to read PHY 12 C22 reg 31: -1
[MCU2_0]   1143.214424 s: EnetPhyMdioDflt_readC22: PHY 12: Failed to read C22 reg: -1
[MCU2_0]   1143.214487 s: EnetPhy_readReg: PHY 12: Failed to read reg 31: -1
[MCU2_0]   1143.214705 s: Mdio_ioctlManualMode: failed to read PHY 0 C22 reg 31: -1
[MCU2_0]   1143.214764 s: EnetPhyMdioDflt_readC22: PHY 0: Failed to read C22 reg: -1
[MCU2_0]   1143.214821 s: EnetPhy_readReg: PHY 0: Failed to read reg 31: -1
[MCU2_0]   1143.214952 s: Mdio_ioctlManualMode: failed to read PHY 3 C22 reg 31: -1
[MCU2_0]   1143.215011 s: EnetPhyMdioDflt_readC22: PHY 3: Failed to read C22 reg: -1
[MCU2_0]   1143.215202 s: EnetPhy_readReg: PHY 3: Failed to read reg 31: -1
[MCU2_0]   1143.314780 s: Mdio_ioctlManualMode: failed to read PHY 0 C22 reg 31: -1
[MCU2_0]   1143.314838 s: EnetPhyMdioDflt_readC22: PHY 0: Failed to read C22 reg: -1
[MCU2_0]   1143.314893 s: EnetPhy_readReg: PHY 0: Failed to read reg 31: -1
[MCU2_0]   1143.315031 s: Mdio_ioctlManualMode: failed to read PHY 3 C22 reg 31: -1
[MCU2_0]   1143.315250 s: EnetPhyMdioDflt_readC22: PHY 3: Failed to read C22 reg: -1
[MCU2_0]   1143.315310 s: EnetPhy_readReg: PHY 3: Failed to read reg 31: -1
[MCU2_0]   1143.614377 s: Mdio_ioctlManualMode: failed to read PHY 12 C22 reg 31: -1
[MCU2_0]   1143.614462 s: EnetPhyMdioDflt_readC22: PHY 12: Failed to read C22 reg: -1
[MCU2_0]   1143.614747 s: Mdio_ioctlManualMode: failed to read PHY 0 C22 reg 31: -1
[MCU2_0]   1143.614807 s: EnetPhyMdioDflt_readC22: PHY 0: Failed to read C22 reg: -1
[MCU2_0]   1143.614862 s: EnetPhy_readReg: PHY 0: Failed to read reg 31: -1
[MCU2_0]   1143.614992 s: Mdio_ioctlManualMode: failed to read PHY 3 C22 reg 31: -1
[MCU2_0]   1143.615167 s: EnetPhyMdioDflt_readC22: PHY 3: Failed to read C22 reg: -1
[MCU2_0]   1143.615243 s: EnetPhy_readReg: PHY 3: Failed to read reg 31: -1
[MCU2_0]   1143.714396 s: Mdio_ioctlManualMode: failed to read PHY 12 C22 reg 31: -1
[MCU2_0]   1143.714481 s: EnetPhyMdioDflt_readC22: PHY 12: Failed to read C22 reg: -1
[MCU2_0]   1143.714545 s: EnetPhy_readReg: PHY 12: Failed to read reg 31: -1
[MCU2_0]   1143.714761 s: Mdio_ioctlManualMode: failed to read PHY 0 C22 reg 31: -1
[MCU2_0]   1143.714823 s: EnetPhyMdioDflt_readC22: PHY 0: Failed to read C22 reg: -1
[MCU2_0]   1143.714879 s: EnetPhy_readReg: PHY 0: Failed to read reg 31: -1
[MCU2_0]   1143.715014 s: Mdio_ioctlManualMode: failed to read PHY 3 C22 reg 31: -1
[MCU2_0]   1143.715207 s: EnetPhyMdioDflt_readC22: PHY 3: Failed to read C22 reg: -1
[MCU2_0]   1143.715280 s: EnetPhy_readReg: PHY 3: Failed to read reg 31: -1
[MCU2_0]   1143.814440 s: Mdio_ioctlManualMode: failed to read PHY 12 C22 reg 31: -1
[MCU2_0]   1143.814531 s: EnetPhyMdioDflt_readC22: PHY 12: Failed to read C22 reg: -1
[MCU2_0]   1143.814594 s: EnetPhy_readReg: PHY 12: Failed to read reg 31: -1
[MCU2_0]   1143.814809 s: Mdio_ioctlManualMode: failed to read PHY 0 C22 reg 31: -1
[MCU2_0]   1143.814871 s: EnetPhyMdioDflt_readC22: PHY 0: Failed to read C22 reg: -1
[MCU2_0]   1143.814925 s: EnetPhy_readReg: PHY 0: Failed to read reg 31: -1
[MCU2_0]   1143.815206 s: Mdio_ioctlManualMode: failed to read PHY 3 C22 reg 31: -1
[MCU2_0]   1143.815285 s: EnetPhyMdioDflt_readC22: PHY 3: Failed to read C22 reg: -1
[MCU2_0]   1143.815346 s: EnetPhy_readReg: PHY 3: Failed to read reg 31: -1
[MCU2_0]   1144.014315 s: Mdio_ioctlManualMode: failed to read PHY 12 C22 reg 31: -1
[MCU2_0]   1144.014406 s: EnetPhyMdioDflt_readC22: PHY 12: Failed to read C22 reg: -1
[MCU2_0]   1144.014470 s: EnetPhy_readReg: PHY 12: Failed to read reg 31: -1
[MCU2_0]   1144.014689 s: Mdio_ioctlManualMode: failed to read PHY 0 C22 reg 31: -1
[MCU2_0]   1144.014752 s: EnetPhyMdioDflt_readC22: PHY 0: Failed to read C22 reg: -1
[MCU2_0]   1144.014810 s: EnetPhy_readReg: PHY 0: Failed to read reg 31: -1
[MCU2_0]   1144.014945 s: Mdio_ioctlManualMode: failed to read PHY 3 C22 reg 31: -1
[MCU2_0]   1144.015001 s: EnetPhyMdioDflt_readC22: PHY 3: Failed to read C22 reg: -1
[MCU2_0]   1144.015179 s: EnetPhy_readReg: PHY 3: Failed to read reg 31: -1
[MCU2_0]   1144.514298 s: Mdio_ioctlManualMode: failed to read PHY 12 C22 reg 31: -1
[MCU2_0]   1144.514381 s: EnetPhyMdioDflt_readC22: PHY 12: Failed to read C22 reg: -1
[MCU2_0]   1144.514443 s: EnetPhy_rmwReg: PHY 12: Failed to read reg 31: -1
[MCU2_0]   1144.514660 s: Mdio_ioctlManualMode: failed to read PHY 0 C22 reg 31: -1
[MCU2_0]   1144.514723 s: EnetPhyMdioDflt_readC22: PHY 0: Failed to read C22 reg: -1
[MCU2_0]   1144.514782 s: EnetPhy_readReg: PHY 0: Failed to read reg 31: -1
[MCU2_0]   1144.514917 s: Mdio_ioctlManualMode: failed to read PHY 3 C22 reg 31: -1
[MCU2_0]   1144.514973 s: EnetPhyMdioDflt_readC22: PHY 3: Failed to read C22 reg: -1
[MCU2_0]   1144.515027 s: EnetPhy_readReg: PHY 3: Failed to read reg 31: -1
[MCU2_0]   1144.714306 s: Mdio_ioctlManualMode: failed to read PHY 12 C22 reg 31: -1
[MCU2_0]   1144.714396 s: EnetPhyMdioDflt_readC22: PHY 12: Failed to read C22 reg: -1
[MCU2_0]   1144.714461 s: EnetPhy_readReg: PHY 12: Failed to read reg 31: -1
[MCU2_0]   1144.714677 s: Mdio_ioctlManualMode: failed to read PHY 0 C22 reg 31: -1
[MCU2_0]   1144.714742 s: EnetPhyMdioDflt_readC22: PHY 0: Failed to read C22 reg: -1
[MCU2_0]   1144.714798 s: EnetPhy_readReg: PHY 0: Failed to read reg 31: -1

     Could you give us some advices?

Best Regards,

Zhang

Hi,

Can you please share full MCU2_0 log?

Above both issues are related to same, PHY0 is failed to read the register while checking for the PHY capabilities.

Please refer to PHY State machine from PHY Integration Guide.

Also, is above issue is observed always or only observed some times.

Can you please share the changes you have made in EthFw for review?

Best Regards,
Sudheer

HI,Sudheer

     Thanks for your support. Sorry to get back to you so late because of the Spring Festival holiday.

     1. We refer to GESI board for hardware design, and don't make change on hardware. So this is four port on CPSW9G. The schematic diagram is as follows:

  4382.CPSW9G.rar

      2. we add application on MCU domain. So we use WKUP_i2c mcu_i2c mcu_uart on MCU domain. Now we found after we add application on MCU Domain the phy15 can't found and phy0 is not alive. Now we're still trying to figure out why?

     3.On the basis of the above, we are using port3  to test our network service.Network structure is shown in figure:

       Can CPSW9G be used with the other switch?

    Now we found a question as log:

root@j7-evm:/opt/vision_apps# source ./vision_apps_init.sh 
root@j7-evm:/opt/vision_apps# [MCU2_0]      3.869061 s: CIO: Init ... Done !!!
[MCU2_0]      3.869131 s: ### CPU Frequency = 1000000000 Hz
[MCU2_0]      3.869173 s: CPU is running FreeRTOS
[MCU2_0]      3.869197 s: APP: Init ... !!!
[MCU2_0]      3.869219 s: SCICLIENT: Init ... !!!
[MCU2_0]      3.869483 s: SCICLIENT: DMSC FW version [8.6.3--v08.06.03 (Chill Capybar]
[MCU2_0]      3.869534 s: SCICLIENT: DMSC FW revision 0x8  
[MCU2_0]      3.869566 s: SCICLIENT: DMSC FW ABI revision 3.1
[MCU2_0]      3.869602 s: SCICLIENT: Init ... Done !!!
[MCU2_0]      3.869628 s: UDMA: Init ... !!!
[MCU2_0]      3.871339 s: UDMA: Init ... Done !!!
[MCU2_0]      3.871399 s: MEM: Init ... !!!
[MCU2_0]      3.871440 s: MEM: Created heap (DDR_LOCAL_MEM, id=0, flags=0x00000004) @ d9000000 of size 16777216 bytes !!!
[MCU2_0]      3.871516 s: MEM: Created heap (L3_MEM, id=1, flags=0x00000000) @ 3600000 of size 262144 bytes !!!
[MCU2_0]      3.871577 s: MEM: Init ... Done !!!
[MCU2_0]      3.871602 s: IPC: Init ... !!!
[MCU2_0]      3.871662 s: IPC: 8 CPUs participating in IPC !!!
[MCU2_0]      3.871710 s: IPC: Waiting for HLOS to be ready ... !!!
[MCU2_0]     13.534331 s: IPC: HLOS is ready !!!
[MCU2_0]     13.555524 s: IPC: Init ... Done !!!
[MCU2_0]     13.555588 s: APP: Syncing with 7 CPUs ... !!!
[MCU2_0]     14.227416 s: APP: Syncing with 7 CPUs ... Done !!!
[MCU2_0]     14.227648 s: REMOTE_SERVICE: Init ... !!!
[MCU2_0]     14.229365 s: REMOTE_SERVICE: Init ... Done !!!
[MCU2_0]     14.229431 s: ETHFW: Init ... !!!
[MCU2_0]     14.337461 s: Warning: Using 6 MAC address(es) from static pool
[MCU2_0]     14.337573 s: ETHFW: Shared multicasts (software fanout):
[MCU2_0]     14.337618 s: ETHFW: Reserved multicasts:
[MCU2_0]     14.337645 s:   01:80:c2:00:00:0e
[MCU2_0]     14.337690 s:   01:1b:19:00:00:00
[MCU2_0]     14.337934 s: EnetMcm: CPSW_9G on MAIN NAVSS
[MCU2_0]     14.345371 s: Mdio_open: MDIO manual mode enabled
[MCU2_0]     14.348041 s: PHY 0 is alive
[MCU2_0]     14.348330 s: PHY 3 is alive
[MCU2_0]     14.348973 s: PHY 12 is alive
[MCU2_0]     14.350655 s: EnetPhy_bindDriver: PHY 12: OUI:080028 Model:23 Ver:01 <-> 'dp83867' : OK
[MCU2_0]     14.351161 s: EnetPhy_bindDriver: PHY 0: OUI:080028 Model:23 Ver:01 <-> 'dp83867' : OK
[MCU2_0]     14.351640 s: EnetPhy_bindDriver: PHY 3: OUI:080028 Model:23 Ver:01 <-> 'dp83867' : OK
[MCU2_0]     14.354204 s: 
[MCU2_0] ETHFW Version   : 0.02.00
[MCU2_0]     14.354280 s: ETHFW Build Date: Jan  8, 2024
[MCU2_0]     14.354314 s: ETHFW Build Time: 19:40:53
[MCU2_0]     14.354340 s: ETHFW Commit SHA: 5994a127
[MCU2_0]     14.354409 s: ETHFW: Init ... DONE !!!
[MCU2_0]     14.354441 s: ETHFW: Remove server Init ... !!!
[MCU2_0]     14.354622 s: CpswProxyServer: Virtual port configuration:
[MCU2_0]     14.354673 s:   mpu_1_0 <-> Switch port 0: mpu_1_0_ethswitch-device-0
[MCU2_0]     14.354716 s:   mcu_2_1 <-> Switch port 1: mcu_2_1_ethswitch-device-1
[MCU2_0]     14.354756 s:   mpu_1_0 <-> MAC port 6: mpu_1_0_ethmac-device-6
[MCU2_0]     14.354809 s:   mcu_2_1 <-> MAC port 7: mcu_2_1_ethmac-device-7
[MCU2_0]     14.355844 s: CpswProxyServer: initialization completed (core: mcu2_0)
[MCU2_0]     14.355911 s: ETHFW: Remove server Init ... DONE !!!
[MCU2_0]     14.357092 s: Starting lwIP, local interface IP is dhcp-enabled
[MCU2_0]     14.365248 s: Host MAC address: 70:ff:76:1d:92:c3
[MCU2_0]     14.369500 s: [LWIPIF_LWIP] Enet LLD netif initialized successfully
[MCU2_0]     14.369595 s: Added interface 'ti1', IP is 0.0.0.0
[MCU2_0]     14.405796 s: FVID2: Init ... !!!
[MCU2_0]     14.405911 s: FVID2: Init ... Done !!!
[MCU2_0]     14.405966 s: DSS: Init ... !!!
[MCU2_0]     14.405993 s: DSS: Display type is eDP !!!
[MCU2_0]     14.406020 s: DSS: M2M Path is enabled !!!
[MCU2_0]     14.406046 s: DSS: SoC init ... !!!
[MCU2_0]     14.406068 s: SCICLIENT: Sciclient_pmSetModuleState module=152 state=2
[MCU2_0]     14.406328 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]     14.406370 s: SCICLIENT: Sciclient_pmSetModuleState module=297 state=2
[MCU2_0]     14.406571 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]     14.406606 s: SCICLIENT: Sciclient_pmSetModuleState module=151 state=2
[MCU2_0]     14.406876 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]     14.406931 s: SCICLIENT: Sciclient_pmSetModuleClkParent module=152 clk=9 parent=11
[MCU2_0]     14.407084 s: SCICLIENT: Sciclient_pmSetModuleClkParent success
[MCU2_0]     14.407120 s: SCICLIENT: Sciclient_pmSetModuleClkParent module=152 clk=13 parent=18
[MCU2_0]     14.407247 s: SCICLIENT: Sciclient_pmSetModuleClkParent success
[MCU2_0]     14.407280 s: SCICLIENT: Sciclient_pmSetModuleClkParent module=152 clk=1 parent=2
[MCU2_0]     14.407386 s: SCICLIENT: Sciclient_pmSetModuleClkParent success
[MCU2_0]     14.407419 s: SCICLIENT: Sciclient_pmSetModuleClkFreq module=152 clk=1 freq=148500000
[MCU2_0]     14.408820 s: SCICLIENT: Sciclient_pmSetModuleClkFreq success
[MCU2_0]     14.408871 s: SCICLIENT: Sciclient_pmModuleClkRequest module=152 clk=1 state=2 flag=0
[MCU2_0]     14.409040 s: SCICLIENT: Sciclient_pmModuleClkRequest success
[MCU2_0]     14.409079 s: DSS: SoC init ... Done !!!
[MCU2_0]     14.409107 s: DSS: Board init ... !!!
[MCU2_0]     14.409130 s: DSS: Board init ... Done !!!
[MCU2_0]     14.429009 s: DSS: Init ... Done !!!
[MCU2_0]     14.429075 s: VHWA: VPAC Init ... !!!
[MCU2_0]     14.429106 s: SCICLIENT: Sciclient_pmSetModuleState module=290 state=2
[MCU2_0]     14.429353 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]     14.429394 s: VHWA: LDC Init ... !!!
[MCU2_0]     14.432854 s: Function:CpswProxyServer_attachExtHandlerCb,HostId:0,CpswType:6
[MCU2_0]     14.433510 s: VHWA: LDC Init ... Done !!!
[MCU2_0]     14.433569 s: VHWA: MSC Init ... !!!
[MCU2_0]     14.446873 s: VHWA: MSC Init ... Done !!!
[MCU2_0]     14.446944 s: VHWA: NF Init ... !!!
[MCU2_0]     14.449078 s: VHWA: NF Init ... Done !!!
[MCU2_0]     14.449141 s: VHWA: VISS Init ... !!!
[MCU2_0]     14.461110 s: VHWA: VISS Init ... Done !!!
[MCU2_0]     14.461178 s: VHWA: VPAC Init ... Done !!!
[MCU2_0]     14.461222 s:  VX_ZONE_INIT:Enabled
[MCU2_0]     14.461252 s:  VX_ZONE_ERROR:Enabled
[MCU2_0]     14.461279 s:  VX_ZONE_WARNING:Enabled
[MCU2_0]     14.462983 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target MCU2-0 
[MCU2_0]     14.463249 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target VPAC_NF 
[MCU2_0]     14.463482 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target VPAC_LDC1 
[MCU2_0]     14.463719 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target VPAC_MSC1 
[MCU2_0]     14.464142 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target VPAC_MSC2 
[MCU2_0]     14.464432 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target VPAC_VISS1 
[MCU2_0]     14.464692 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target CAPTURE1 
[MCU2_0]     14.465090 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target CAPTURE2 
[MCU2_0]     14.465380 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target DISPLAY1 
[MCU2_0]     14.465661 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target DISPLAY2 
[MCU2_0]     14.466037 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target CSITX 
[MCU2_0]     14.466337 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target CAPTURE3 
[MCU2_0]     14.466610 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target CAPTURE4 
[MCU2_0]     14.467000 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target CAPTURE5 
[MCU2_0]     14.467298 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target CAPTURE6 
[MCU2_0]     14.467562 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target CAPTURE7 
[MCU2_0]     14.467930 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target CAPTURE8 
[MCU2_0]     14.468189 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target DSS_M2M1 
[MCU2_0]     14.468440 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target DSS_M2M2 
[MCU2_0]     14.468681 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target DSS_M2M3 
[MCU2_0]     14.469078 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target DSS_M2M4 
[MCU2_0]     14.469140 s:  VX_ZONE_INIT:[tivxInitLocal:130] Initialization Done !!!
[MCU2_0]     14.469175 s: APP: OpenVX Target kernel init ... !!!
[MCU2_0]     14.490284 s: APP: OpenVX Target kernel init ... Done !!!
[MCU2_0]     14.490350 s: CSI2RX: Init ... !!!
[MCU2_0]     14.490376 s: SCICLIENT: Sciclient_pmSetModuleState module=25 state=2
[MCU2_0]     14.490525 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]     14.490568 s: SCICLIENT: Sciclient_pmSetModuleState module=26 state=2
[MCU2_0]     14.490752 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]     14.490895 s: SCICLIENT: Sciclient_pmSetModuleState module=27 state=2
[MCU2_0]     14.491073 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]     14.491110 s: SCICLIENT: Sciclient_pmSetModuleState module=147 state=2
[MCU2_0]     14.491229 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]     14.491261 s: SCICLIENT: Sciclient_pmSetModuleState module=148 state=2
[MCU2_0]     14.491356 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]     14.491587 s: CSI2RX: Init ... Done !!!
[MCU2_0]     14.491626 s: CSI2TX: Init ... !!!
[MCU2_0]     14.491651 s: SCICLIENT: Sciclient_pmSetModuleState module=25 state=2
[MCU2_0]     14.491756 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]     14.491916 s: SCICLIENT: Sciclient_pmSetModuleState module=28 state=2
[MCU2_0]     14.492081 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]     14.492118 s: SCICLIENT: Sciclient_pmSetModuleState module=296 state=2
[MCU2_0]     14.492266 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]     14.492370 s: CSI2TX: Init ... Done !!!
[MCU2_0]     14.492407 s: ISS: Init ... !!!
[MCU2_0]     14.492446 s: IssSensor_Init ... Done !!!
[MCU2_0]     14.492529 s: IttRemoteServer_Init ... Done !!!
[MCU2_0]     14.492564 s: VISS REMOTE SERVICE: Init ... !!!
[MCU2_0]     14.492629 s: VISS REMOTE SERVICE: Init ... Done !!!
[MCU2_0]     14.492660 s: UDMA Copy: Init ... !!!
[MCU2_0]     14.495183 s: UDMA Copy: Init ... Done !!!
[MCU2_0]     14.495293 s: APP: Init ... Done !!!
[MCU2_0]     14.495327 s: APP: Run ... !!!
[MCU2_0]     14.495350 s: IPC: Starting echo test ...
[MCU2_0]     14.499230 s: APP: Run ... Done !!!
[MCU2_0]     14.501656 s: IPC: Echo status: mpu1_0[x] mcu2_0[s] mcu2_1[P] mcu3_0[.] mcu3_1[.] C66X_1[.] C66X_2[.] C7X_1[.] 
[MCU2_0]     14.501956 s: IPC: Echo status: mpu1_0[x] mcu2_0[s] mcu2_1[P] mcu3_0[P] mcu3_1[.] C66X_1[.] C66X_2[.] C7X_1[.] 
[MCU2_0]     14.502090 s: IPC: Echo status: mpu1_0[x] mcu2_0[s] mcu2_1[P] mcu3_0[P] mcu3_1[P] C66X_1[.] C66X_2[.] C7X_1[.] 
[MCU2_0]     14.502204 s: IPC: Echo status: mpu1_0[x] mcu2_0[s] mcu2_1[P] mcu3_0[P] mcu3_1[P] C66X_1[P] C66X_2[.] C7X_1[.] 
[MCU2_0]     14.502311 s: IPC: Echo status: mpu1_0[x] mcu2_0[s] mcu2_1[P] mcu3_0[P] mcu3_1[P] C66X_1[P] C66X_2[P] C7X_1[.] 
[MCU2_0]     14.502417 s: IPC: Echo status: mpu1_0[x] mcu2_0[s] mcu2_1[P] mcu3_0[P] mcu3_1[P] C66X_1[P] C66X_2[P] C7X_1[P] 
[MCU2_0]     14.536031 s: Function:CpswProxyServer_attachExtHandlerCb,HostId:0,CpswType:6
[MCU2_0]     15.535876 s: Assertion @ Line: 1212 in enet_mcm.c: false : failed !!!
[MCU2_0]     16.701821 s: Function:CpswProxyServer_registerMacHandlerCb,HostId:0,Handle:a3ac5f84,CoreKey:38acb7e6, MacAddress:70:ff:76:1d:92:c2, FlowIdx:173, FlowIdxOffset:1
[MCU2_0]     16.717434 s: Function:CpswProxyServer_setPromiscModeHandlerCb,HostId:0,Handle:a3ac5f84,CoreKey:38acb7e6,mode:disable
[MCU2_0]     16.717723 s: Function:CpswProxyServer_setPromiscModeHandlerCb,HostId:0,Handle:a3ac5f84,CoreKey:38acb7e6,mode:disable
[MCU2_0]     16.728167 s: Function:CpswProxyServer_setPromiscModeHandlerCb,HostId:0,Handle:a3ac5f84,CoreKey:38acb7e6,mode:disable
[MCU2_0]     16.739218 s: Function:CpswProxyServer_registerMacHandlerCb,HostId:0,Handle:a3ac5f84,CoreKey:38acb7e6, MacAddress:70:ff:76:1d:92:c1, FlowIdx:172, FlowIdxOffset:0
[MCU2_0]     16.742408 s: Cpsw_ioctlInternal: CPSW: Registered MAC address. ALE entry:7, Policer Entry:2
[MCU2_0]     16.750853 s: Function:CpswProxyServer_filterAddMacHandlerCb,HostId:0,Handle:a3ac5f84,CoreKey:38acb7e6, MacAddress:33:33:0:0:0:1, vlanId:0, FlowIdx:172, FlowIdOffset:0
[MCU2_0]     16.755208 s: Function:CpswProxyServer_filterAddMacHandlerCb,HostId:0,Handle:a3ac5f84,CoreKey:38acb7e6, MacAddress:1:0:5e:0:0:1, vlanId:0, FlowIdx:172, FlowIdOffset:0
[MCU2_0]     16.758849 s: Function:CpswProxyServer_filterAddMacHandlerCb,HostId:0,Handle:a3ac5f84,CoreKey:38acb7e6, MacAddress:33:33:ff:1d:92:c1, vlanId:0, FlowIdx:172, FlowIdOffset:0
[MCU2_0]     16.976708 s: Function:CpswProxyServer_setPromiscModeHandlerCb,HostId:0,Handle:a3ac5f84,CoreKey:38acb7e6,mode:disable
[MCU2_0]     16.977142 s: Function:CpswProxyServer_setPromiscModeHandlerCb,HostId:0,Handle:a3ac5f84,CoreKey:38acb7e6,mode:disable
[MCU2_0]     17.033403 s: Function:CpswProxyServer_filterAddMacHandlerCb,HostId:0,Handle:a3ac5f84,CoreKey:38acb7e6, MacAddress:1:80:c2:0:0:0, vlanId:0, FlowIdx:172, FlowIdOffset:0
[MCU2_0]     17.036878 s: Function:CpswProxyServer_filterAddMacHandlerCb,HostId:0,Handle:a3ac5f84,CoreKey:38acb7e6, MacAddress:1:80:c2:0:0:3, vlanId:0, FlowIdx:172, FlowIdOffset:0
[MCU2_0]     17.040307 s: Function:CpswProxyServer_filterAddMacHandlerCb,HostId:0,Handle:a3ac5f84,CoreKey:38acb7e6, MacAddress:1:80:c2:0:0:e, vlanId:0, FlowIdx:172, FlowIdOffset:0
[MCU2_0]     17.040457 s: CpswProxyServer_isRsvdMcast: Reserved mcast cannot be added to filter
[MCU2_0]     17.117712 s: Function:CpswProxyServer_setPromiscModeHandlerCb,HostId:0,Handle:a3ac5f84,CoreKey:38acb7e6,mode:disable
[MCU2_0]     17.117959 s: Function:CpswProxyServer_filterAddMacHandlerCb,HostId:0,Handle:a3ac5f84,CoreKey:38acb7e6, MacAddress:33:33:0:0:0:fb, vlanId:0, FlowIdx:172, FlowIdOffset:0
[MCU2_0]     18.013672 s: Function:CpswProxyServer_filterAddMacHandlerCb,HostId:0,Handle:a3ac5f84,CoreKey:38acb7e6, MacAddress:33:33:0:1:0:3, vlanId:0, FlowIdx:172, FlowIdOffset:0
[MCU2_0]     18.480823 s: Function:CpswProxyServer_setPromiscModeHandlerCb,HostId:0,Handle:a3ac5f84,CoreKey:38acb7e6,mode:disable
[MCU2_0]     20.273118 s: Function:CpswProxyServer_unregisterMacHandlerCb,HostId:0,Handle:a3ac5f84,CoreKey:38acb7e6, MacAddress:70:ff:76:1d:92:c1, FlowIdx:172, FlowIdOffset:0
[MCU2_0]     20.273593 s: Function:CpswProxyServer_filterDelMacHandlerCb,HostId:0,Handle:a3ac5f84,CoreKey:38acb7e6, MacAddress:33:33:0:0:0:1, vlanId:0, FlowIdx:172, FlowIdOffset:0
[MCU2_0]     20.274090 s: Function:CpswProxyServer_filterDelMacHandlerCb,HostId:0,Handle:a3ac5f84,CoreKey:38acb7e6, MacAddress:1:0:5e:0:0:1, vlanId:0, FlowIdx:172, FlowIdOffset:0
[MCU2_0]     20.274467 s: Function:CpswProxyServer_filterDelMacHandlerCb,HostId:0,Handle:a3ac5f84,CoreKey:38acb7e6, MacAddress:33:33:ff:1d:92:c1, vlanId:0, FlowIdx:172, FlowIdOffset:0
[MCU2_0]     20.274903 s: Function:CpswProxyServer_filterDelMacHandlerCb,HostId:0,Handle:a3ac5f84,CoreKey:38acb7e6, MacAddress:1:80:c2:0:0:0, vlanId:0, FlowIdx:172, FlowIdOffset:0
[MCU2_0]     20.275335 s: Function:CpswProxyServer_filterDelMacHandlerCb,HostId:0,Handle:a3ac5f84,CoreKey:38acb7e6, MacAddress:1:80:c2:0:0:3, vlanId:0, FlowIdx:172, FlowIdOffset:0
[MCU2_0]     20.275714 s: Function:CpswProxyServer_filterDelMacHandlerCb,HostId:0,Handle:a3ac5f84,CoreKey:38acb7e6, MacAddress:1:80:c2:0:0:e, vlanId:0, FlowIdx:172, FlowIdOffset:0
[MCU2_0]     20.275919 s: CpswProxyServer_isRsvdMcast: Reserved mcast cannot be added to filter
[MCU2_0]     20.276162 s: Function:CpswProxyServer_filterDelMacHandlerCb,HostId:0,Handle:a3ac5f84,CoreKey:38acb7e6, MacAddress:33:33:0:0:0:fb, vlanId:0, FlowIdx:172, FlowIdOffset:0
[MCU2_0]     20.276548 s: Function:CpswProxyServer_filterDelMacHandlerCb,HostId:0,Handle:a3ac5f84,CoreKey:38acb7e6, MacAddress:33:33:0:1:0:3, vlanId:0, FlowIdx:172, FlowIdOffset:0
[MCU2_0]     20.403643 s: Function:CpswProxyServer_setPromiscModeHandlerCb,HostId:0,Handle:a3ac5f84,CoreKey:38acb7e6,mode:disable
[MCU2_0]     20.403883 s: Function:CpswProxyServer_unregisterMacHandlerCb,HostId:0,Handle:a3ac5f84,CoreKey:38acb7e6, MacAddress:70:ff:76:1d:92:c2, FlowIdx:173, FlowIdOffset:1
[MCU2_0]     21.532485 s: Function:CpswProxyServer_registerIpv4MacHandlerCb,HostId:0,Handle:a3ac5f84,CoreKey:38acb7e6, MacAddress:70:ff:76:1d:92:c1 IPv4Addr:192.168.1.205
[MCU2_0]     21.532661 s: 
[MCU2_0]  SNo.      IP Address          MAC Address   
[MCU2_0]     21.532704 s: ------    -------------     -----------------
[MCU2_0]     21.532741 s:   1       192.168.1.205     70:ff:76:1d:92:c1
[MCU2_0]     21.533883 s: Function:CpswProxyServer_registerMacHandlerCb,HostId:0,Handle:a3ac5f84,CoreKey:38acb7e6, MacAddress:70:ff:76:1d:92:c1, FlowIdx:172, FlowIdxOffset:0
[MCU2_0]     21.537020 s: Cpsw_ioctlInternal: CPSW: Registered MAC address. ALE entry:6, Policer Entry:1
[MCU2_0]     21.552914 s: Function:CpswProxyServer_filterAddMacHandlerCb,HostId:0,Handle:a3ac5f84,CoreKey:38acb7e6, MacAddress:1:0:5e:0:0:1, vlanId:0, FlowIdx:172, FlowIdOffset:0
[MCU2_0]     21.556356 s: Function:CpswProxyServer_filterAddMacHandlerCb,HostId:0,Handle:a3ac5f84,CoreKey:38acb7e6, MacAddress:1:0:5e:0:0:fb, vlanId:0, FlowIdx:172, FlowIdOffset:0
[MCU2_0]     21.559843 s: Function:CpswProxyServer_filterAddMacHandlerCb,HostId:0,Handle:a3ac5f84,CoreKey:38acb7e6, MacAddress:1:80:c2:0:0:0, vlanId:0, FlowIdx:172, FlowIdOffset:0
[MCU2_0]     21.563113 s: Function:CpswProxyServer_registerMacHandlerCb,HostId:0,Handle:a3ac5f84,CoreKey:38acb7e6, MacAddress:70:ff:76:1d:92:c2, FlowIdx:173, FlowIdxOffset:1
[MCU2_0]     21.565055 s: Function:CpswProxyServer_filterAddMacHandlerCb,HostId:0,Handle:a3ac5f84,CoreKey:38acb7e6, MacAddress:1:80:c2:0:0:3, vlanId:0, FlowIdx:172, FlowIdOffset:0
[MCU2_0]     21.568569 s: CpswProxyServer_isRsvdMcast: Reserved mcast cannot be added to filter
[MCU2_1]      3.812888 s: CIO: Init ... Done !!!
[MCU2_1]      3.812961 s: ### CPU Frequency = 1000000000 Hz
[MCU2_1]      3.813004 s: CPU is running FreeRTOS
[MCU2_1]      3.813031 s: APP: Init ... !!!
[MCU2_1]      3.813055 s: SCICLIENT: Init ... !!!
[MCU2_1]      3.813334 s: SCICLIENT: DMSC FW version [8.6.3--v08.06.03 (Chill Capybar]
[MCU2_1]      3.813405 s: SCICLIENT: DMSC FW revision 0x8  
[MCU2_1]      3.813443 s: SCICLIENT: DMSC FW ABI revision 3.1
[MCU2_1]      3.813481 s: SCICLIENT: Init ... Done !!!
[MCU2_1]      3.813510 s: UDMA: Init ... !!!
[MCU2_1]      3.815575 s: UDMA: Init ... Done !!!
[MCU2_1]      3.815642 s: MEM: Init ... !!!
[MCU2_1]      3.815686 s: MEM: Created heap (DDR_LOCAL_MEM, id=0, flags=0x00000004) @ da000000 of size 16777216 bytes !!!
[MCU2_1]      3.815764 s: MEM: Created heap (L3_MEM, id=1, flags=0x00000001) @ 3640000 of size 262144 bytes !!!
[MCU2_1]      3.815825 s: MEM: Init ... Done !!!
[MCU2_1]      3.815851 s: IPC: Init ... !!!
[MCU2_1]      3.815915 s: IPC: 8 CPUs participating in IPC !!!
[MCU2_1]      3.815967 s: IPC: Waiting for HLOS to be ready ... !!!
[MCU2_1]     13.777722 s: IPC: HLOS is ready !!!
[MCU2_1]     13.798854 s: IPC: Init ... Done !!!
[MCU2_1]     13.798922 s: APP: Syncing with 7 CPUs ... !!!
[MCU2_1]     14.227414 s: APP: Syncing with 7 CPUs ... Done !!!
[MCU2_1]     14.227650 s: REMOTE_SERVICE: Init ... !!!
[MCU2_1]     14.229372 s: REMOTE_SERVICE: Init ... Done !!!
[MCU2_1]     14.229454 s: FVID2: Init ... !!!
[MCU2_1]     14.229525 s: FVID2: Init ... Done !!!
[MCU2_1]     14.229562 s: VHWA: DMPAC: Init ... !!!
[MCU2_1]     14.229589 s: SCICLIENT: Sciclient_pmSetModuleState module=48 state=2
[MCU2_1]     14.230145 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_1]     14.230189 s: SCICLIENT: Sciclient_pmSetModuleState module=305 state=2
[MCU2_1]     14.230724 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_1]     14.230765 s: VHWA: DOF Init ... !!!
[MCU2_1]     14.239835 s: VHWA: DOF Init ... Done !!!
[MCU2_1]     14.239903 s: VHWA: SDE Init ... !!!
[MCU2_1]     14.242706 s: VHWA: SDE Init ... Done !!!
[MCU2_1]     14.242766 s: VHWA: DMPAC: Init ... Done !!!
[MCU2_1]     14.242816 s:  VX_ZONE_INIT:Enabled
[MCU2_1]     14.242849 s:  VX_ZONE_ERROR:Enabled
[MCU2_1]     14.242875 s:  VX_ZONE_WARNING:Enabled
[MCU2_1]     14.244285 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target MCU2-1 
[MCU2_1]     14.244546 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target DMPAC_SDE 
[MCU2_1]     14.244775 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target DMPAC_DOF 
[MCU2_1]     14.244834 s:  VX_ZONE_INIT:[tivxInitLocal:130] Initialization Done !!!
[MCU2_1]     14.244872 s: APP: OpenVX Target kernel init ... !!!
[MCU2_1]     14.245155 s: APP: OpenVX Target kernel init ... Done !!!
[MCU2_1]     14.245199 s: UDMA Copy: Init ... !!!
[MCU2_1]     14.247074 s: UDMA Copy: Init ... Done !!!
[MCU2_1]     14.247145 s: APP: Init ... Done !!!
[MCU2_1]     14.247179 s: APP: Run ... !!!
[MCU2_1]     14.247205 s: IPC: Starting echo test ...
[MCU2_1]     14.250607 s: APP: Run ... Done !!!
[MCU2_1]     14.252234 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[s] mcu3_0[.] mcu3_1[.] C66X_1[P] C66X_2[.] C7X_1[.] 
[MCU2_1]     14.252361 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[s] mcu3_0[P] mcu3_1[.] C66X_1[P] C66X_2[.] C7X_1[.] 
[MCU2_1]     14.252487 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[s] mcu3_0[P] mcu3_1[P] C66X_1[P] C66X_2[.] C7X_1[.] 
[MCU2_1]     14.252592 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[s] mcu3_0[P] mcu3_1[P] C66X_1[P] C66X_2[P] C7X_1[.] 
[MCU2_1]     14.252696 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[s] mcu3_0[P] mcu3_1[P] C66X_1[P] C66X_2[P] C7X_1[P] 
[MCU2_1]     14.501578 s: IPC: Echo status: mpu1_0[x] mcu2_0[P] mcu2_1[s] mcu3_0[P] mcu3_1[P] C66X_1[P] C66X_2[P] C7X_1[P] 
[MCU3_0]      3.844181 s: CIO: Init ... Done !!!
[MCU3_0]      3.844246 s: ### CPU Frequency = 1000000000 Hz
[MCU3_0]      3.844288 s: CPU is running FreeRTOS
[MCU3_0]      3.844313 s: APP: Init ... !!!
[MCU3_0]      3.844336 s: SCICLIENT: Init ... !!!
[MCU3_0]      3.844613 s: SCICLIENT: DMSC FW version [8.6.3--v08.06.03 (Chill Capybar]
[MCU3_0]      3.844668 s: SCICLIENT: DMSC FW revision 0x8  
[MCU3_0]      3.844724 s: SCICLIENT: DMSC FW ABI revision 3.1
[MCU3_0]      3.844763 s: SCICLIENT: Init ... Done !!!
[MCU3_0]      3.844791 s: MEM: Init ... !!!
[MCU3_0]      3.844828 s: MEM: Created heap (DDR_LOCAL_MEM, id=0, flags=0x00000004) @ db000000 of size 8388608 bytes !!!
[MCU3_0]      3.844895 s: MEM: Init ... Done !!!
[MCU3_0]      3.844921 s: IPC: Init ... !!!
[MCU3_0]      3.844980 s: IPC: 8 CPUs participating in IPC !!!
[MCU3_0]      3.845033 s: IPC: Waiting for HLOS to be ready ... !!!
[MCU3_0]     14.081532 s: IPC: HLOS is ready !!!
[MCU3_0]     14.102894 s: IPC: Init ... Done !!!
[MCU3_0]     14.102961 s: APP: Syncing with 7 CPUs ... !!!
[MCU3_0]     14.227414 s: APP: Syncing with 7 CPUs ... Done !!!
[MCU3_0]     14.227469 s: REMOTE_SERVICE: Init ... !!!
[MCU3_0]     14.229523 s: REMOTE_SERVICE: Init ... Done !!!
[MCU3_0]     14.229599 s:  VX_ZONE_INIT:Enabled
[MCU3_0]     14.229630 s:  VX_ZONE_ERROR:Enabled
[MCU3_0]     14.229654 s:  VX_ZONE_WARNING:Enabled
[MCU3_0]     14.230963 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target MCU3-0 
[MCU3_0]     14.231029 s:  VX_ZONE_INIT:[tivxInitLocal:130] Initialization Done !!!
[MCU3_0]     14.231064 s: APP: OpenVX Target kernel init ... !!!
[MCU3_0]     14.231092 s: APP: OpenVX Target kernel init ... Done !!!
[MCU3_0]     14.231121 s: APP: Init ... Done !!!
[MCU3_0]     14.231146 s: APP: Run ... !!!
[MCU3_0]     14.231168 s: IPC: Starting echo test ...
[MCU3_0]     14.234576 s: APP: Run ... Done !!!
[MCU3_0]     14.236264 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[s] mcu3_1[.] C66X_1[.] C66X_2[.] C7X_1[P] 
[MCU3_0]     14.236387 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[s] mcu3_1[.] C66X_1[P] C66X_2[.] C7X_1[P] 
[MCU3_0]     14.236592 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[s] mcu3_1[.] C66X_1[P] C66X_2[P] C7X_1[P] 
[MCU3_0]     14.236847 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[s] mcu3_1[P] C66X_1[P] C66X_2[P] C7X_1[P] 
[MCU3_0]     14.251400 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[P] mcu3_0[s] mcu3_1[P] C66X_1[P] C66X_2[P] C7X_1[P] 
[MCU3_0]     14.501600 s: IPC: Echo status: mpu1_0[x] mcu2_0[P] mcu2_1[P] mcu3_0[s] mcu3_1[P] C66X_1[P] C66X_2[P] C7X_1[P] 
[MCU3_1]      3.877506 s: CIO: Init ... Done !!!
[MCU3_1]      3.877574 s: ### CPU Frequency = 1000000000 Hz
[MCU3_1]      3.877614 s: CPU is running FreeRTOS
[MCU3_1]      3.877639 s: APP: Init ... !!!
[MCU3_1]      3.877663 s: SCICLIENT: Init ... !!!
[MCU3_1]      3.877940 s: SCICLIENT: DMSC FW version [8.6.3--v08.06.03 (Chill Capybar]
[MCU3_1]      3.877990 s: SCICLIENT: DMSC FW revision 0x8  
[MCU3_1]      3.878039 s: SCICLIENT: DMSC FW ABI revision 3.1
[MCU3_1]      3.878079 s: SCICLIENT: Init ... Done !!!
[MCU3_1]      3.878107 s: MEM: Init ... !!!
[MCU3_1]      3.878145 s: MEM: Created heap (DDR_LOCAL_MEM, id=0, flags=0x00000004) @ db800000 of size 8388608 bytes !!!
[MCU3_1]      3.878210 s: MEM: Init ... Done !!!
[MCU3_1]      3.878235 s: IPC: Init ... !!!
[MCU3_1]      3.878296 s: IPC: 8 CPUs participating in IPC !!!
[MCU3_1]      3.878345 s: IPC: Waiting for HLOS to be ready ... !!!
[MCU3_1]     14.206104 s: IPC: HLOS is ready !!!
[MCU3_1]     14.227301 s: IPC: Init ... Done !!!
[MCU3_1]     14.227367 s: APP: Syncing with 7 CPUs ... !!!
[MCU3_1]     14.227415 s: APP: Syncing with 7 CPUs ... Done !!!
[MCU3_1]     14.227453 s: REMOTE_SERVICE: Init ... !!!
[MCU3_1]     14.229526 s: REMOTE_SERVICE: Init ... Done !!!
[MCU3_1]     14.229605 s:  VX_ZONE_INIT:Enabled
[MCU3_1]     14.229635 s:  VX_ZONE_ERROR:Enabled
[MCU3_1]     14.229664 s:  VX_ZONE_WARNING:Enabled
[MCU3_1]     14.230975 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target MCU3-1 
[MCU3_1]     14.231049 s:  VX_ZONE_INIT:[tivxInitLocal:130] Initialization Done !!!
[MCU3_1]     14.231088 s: APP: OpenVX Target kernel init ... !!!
[MCU3_1]     14.231118 s: APP: OpenVX Target kernel init ... Done !!!
[MCU3_1]     14.231149 s: APP: Init ... Done !!!
[MCU3_1]     14.231174 s: APP: Run ... !!!
[MCU3_1]     14.231198 s: IPC: Starting echo test ...
[MCU3_1]     14.234621 s: APP: Run ... Done !!!
[MCU3_1]     14.236329 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[.] mcu3_1[s] C66X_1[P] C66X_2[.] C7X_1[.] 
[MCU3_1]     14.236457 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[.] mcu3_1[s] C66X_1[P] C66X_2[.] C7X_1[P] 
[MCU3_1]     14.236660 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[s] C66X_1[P] C66X_2[.] C7X_1[P] 
[MCU3_1]     14.236839 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[s] C66X_1[P] C66X_2[P] C7X_1[P] 
[MCU3_1]     14.251413 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[P] mcu3_0[P] mcu3_1[s] C66X_1[P] C66X_2[P] C7X_1[P] 
[MCU3_1]     14.501618 s: IPC: Echo status: mpu1_0[x] mcu2_0[P] mcu2_1[P] mcu3_0[P] mcu3_1[s] C66X_1[P] C66X_2[P] C7X_1[P] 
[C6x_1 ]      3.919246 s: CIO: Init ... Done !!!
[C6x_1 ]      3.919273 s: ### CPU Frequency = 1350000000 Hz
[C6x_1 ]      3.919283 s: CPU is running FreeRTOS
[C6x_1 ]      3.919291 s: APP: Init ... !!!
[C6x_1 ]      3.919298 s: SCICLIENT: Init ... !!!
[C6x_1 ]      3.919545 s: SCICLIENT: DMSC FW version [8.6.3--v08.06.03 (Chill Capybar]
[C6x_1 ]      3.919556 s: SCICLIENT: DMSC FW revision 0x8  
[C6x_1 ]      3.919565 s: SCICLIENT: DMSC FW ABI revision 3.1
[C6x_1 ]      3.919575 s: SCICLIENT: Init ... Done !!!
[C6x_1 ]      3.919584 s: UDMA: Init ... !!!
[C6x_1 ]      3.921644 s: UDMA: Init ... Done !!!
[C6x_1 ]      3.921663 s: MEM: Init ... !!!
[C6x_1 ]      3.921676 s: MEM: Created heap (DDR_LOCAL_MEM, id=0, flags=0x00000004) @ dc000000 of size 16777216 bytes !!!
[C6x_1 ]      3.921693 s: MEM: Created heap (L2_MEM, id=2, flags=0x00000001) @ 800000 of size 229376 bytes !!!
[C6x_1 ]      3.921709 s: MEM: Created heap (DDR_SCRATCH_MEM, id=4, flags=0x00000001) @ dd000000 of size 50331648 bytes !!!
[C6x_1 ]      3.921725 s: MEM: Init ... Done !!!
[C6x_1 ]      3.921733 s: IPC: Init ... !!!
[C6x_1 ]      3.921754 s: IPC: 8 CPUs participating in IPC !!!
[C6x_1 ]      3.921767 s: IPC: Waiting for HLOS to be ready ... !!!
[C6x_1 ]     12.819947 s: IPC: HLOS is ready !!!
[C6x_1 ]     12.825245 s: IPC: Init ... Done !!!
[C6x_1 ]     12.825276 s: APP: Syncing with 7 CPUs ... !!!
[C6x_1 ]     14.227413 s: APP: Syncing with 7 CPUs ... Done !!!
[C6x_1 ]     14.227428 s: REMOTE_SERVICE: Init ... !!!
[C6x_1 ]     14.228157 s: REMOTE_SERVICE: Init ... Done !!!
[C6x_1 ]     14.228197 s:  VX_ZONE_INIT:Enabled
[C6x_1 ]     14.228208 s:  VX_ZONE_ERROR:Enabled
[C6x_1 ]     14.228219 s:  VX_ZONE_WARNING:Enabled
[C6x_1 ]     14.229122 s:  VX_ZONE_INIT:[tivxInitLocal:130] Initialization Done !!!
[C6x_1 ]     14.229137 s: APP: OpenVX Target kernel init ... !!!
[C6x_1 ]     14.229398 s: APP: OpenVX Target kernel init ... Done !!!
[C6x_1 ]     14.229415 s: UDMA Copy: Init ... !!!
[C6x_1 ]     14.233583 s: UDMA Copy: Init ... Done !!!
[C6x_1 ]     14.233604 s: APP: Init ... Done !!!
[C6x_1 ]     14.233613 s: APP: Run ... !!!
[C6x_1 ]     14.233621 s: IPC: Starting echo test ...
[C6x_1 ]     14.235125 s: APP: Run ... Done !!!
[C6x_1 ]     14.235530 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[.] mcu3_1[.] C66X_1[s] C66X_2[x] C7X_1[P] 
[C6x_1 ]     14.236012 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[.] mcu3_1[.] C66X_1[s] C66X_2[P] C7X_1[P] 
[C6x_1 ]     14.236073 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[.] C66X_1[s] C66X_2[P] C7X_1[P] 
[C6x_1 ]     14.236245 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[P] C66X_1[s] C66X_2[P] C7X_1[P] 
[C6x_1 ]     14.251269 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[P] mcu3_0[P] mcu3_1[P] C66X_1[s] C66X_2[P] C7X_1[P] 
[C6x_1 ]     14.501473 s: IPC: Echo status: mpu1_0[x] mcu2_0[P] mcu2_1[P] mcu3_0[P] mcu3_1[P] C66X_1[s] C66X_2[P] C7X_1[P] 
[C6x_2 ]      4.000063 s: CIO: Init ... Done !!!
[C6x_2 ]      4.000091 s: ### CPU Frequency = 1350000000 Hz
[C6x_2 ]      4.000101 s: CPU is running FreeRTOS
[C6x_2 ]      4.000109 s: APP: Init ... !!!
[C6x_2 ]      4.000117 s: SCICLIENT: Init ... !!!
[C6x_2 ]      4.000348 s: SCICLIENT: DMSC FW version [8.6.3--v08.06.03 (Chill Capybar]
[C6x_2 ]      4.000360 s: SCICLIENT: DMSC FW revision 0x8  
[C6x_2 ]      4.000369 s: SCICLIENT: DMSC FW ABI revision 3.1
[C6x_2 ]      4.000380 s: SCICLIENT: Init ... Done !!!
[C6x_2 ]      4.000389 s: UDMA: Init ... !!!
[C6x_2 ]      4.002460 s: UDMA: Init ... Done !!!
[C6x_2 ]      4.002480 s: MEM: Init ... !!!
[C6x_2 ]      4.002494 s: MEM: Created heap (DDR_LOCAL_MEM, id=0, flags=0x00000004) @ e0000000 of size 16777216 bytes !!!
[C6x_2 ]      4.002512 s: MEM: Created heap (L2_MEM, id=2, flags=0x00000001) @ 800000 of size 229376 bytes !!!
[C6x_2 ]      4.002527 s: MEM: Created heap (DDR_SCRATCH_MEM, id=4, flags=0x00000001) @ e1000000 of size 50331648 bytes !!!
[C6x_2 ]      4.002543 s: MEM: Init ... Done !!!
[C6x_2 ]      4.002552 s: IPC: Init ... !!!
[C6x_2 ]      4.002574 s: IPC: 8 CPUs participating in IPC !!!
[C6x_2 ]      4.002588 s: IPC: Waiting for HLOS to be ready ... !!!
[C6x_2 ]     12.985362 s: IPC: HLOS is ready !!!
[C6x_2 ]     12.990428 s: IPC: Init ... Done !!!
[C6x_2 ]     12.990455 s: APP: Syncing with 7 CPUs ... !!!
[C6x_2 ]     14.227413 s: APP: Syncing with 7 CPUs ... Done !!!
[C6x_2 ]     14.227428 s: REMOTE_SERVICE: Init ... !!!
[C6x_2 ]     14.228170 s: REMOTE_SERVICE: Init ... Done !!!
[C6x_2 ]     14.228208 s:  VX_ZONE_INIT:Enabled
[C6x_2 ]     14.228218 s:  VX_ZONE_ERROR:Enabled
[C6x_2 ]     14.228228 s:  VX_ZONE_WARNING:Enabled
[C6x_2 ]     14.229136 s:  VX_ZONE_INIT:[tivxInitLocal:130] Initialization Done !!!
[C6x_2 ]     14.229151 s: APP: OpenVX Target kernel init ... !!!
[C6x_2 ]     14.229414 s: APP: OpenVX Target kernel init ... Done !!!
[C6x_2 ]     14.229431 s: UDMA Copy: Init ... !!!
[C6x_2 ]     14.233970 s: UDMA Copy: Init ... Done !!!
[C6x_2 ]     14.233993 s: APP: Init ... Done !!!
[C6x_2 ]     14.234002 s: APP: Run ... !!!
[C6x_2 ]     14.234012 s: IPC: Starting echo test ...
[C6x_2 ]     14.235592 s: APP: Run ... Done !!!
[C6x_2 ]     14.236026 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[.] mcu3_1[.] C66X_1[P] C66X_2[s] C7X_1[.] 
[C6x_2 ]     14.236066 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[.] mcu3_1[.] C66X_1[P] C66X_2[s] C7X_1[P] 
[C6x_2 ]     14.236187 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[.] C66X_1[P] C66X_2[s] C7X_1[P] 
[C6x_2 ]     14.236268 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[P] C66X_1[P] C66X_2[s] C7X_1[P] 
[C6x_2 ]     14.251306 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[P] mcu3_0[P] mcu3_1[P] C66X_1[P] C66X_2[s] C7X_1[P] 
[C6x_2 ]     14.501501 s: IPC: Echo status: mpu1_0[x] mcu2_0[P] mcu2_1[P] mcu3_0[P] mcu3_1[P] C66X_1[P] C66X_2[s] C7X_1[P] 
[C7x_1 ]      4.222913 s: CIO: Init ... Done !!!
[C7x_1 ]      4.222927 s: ### CPU Frequency = 1000000000 Hz
[C7x_1 ]      4.222938 s: CPU is running FreeRTOS
[C7x_1 ]      4.222946 s: APP: Init ... !!!
[C7x_1 ]      4.222954 s: SCICLIENT: Init ... !!!
[C7x_1 ]      4.223200 s: SCICLIENT: DMSC FW version [8.6.3--v08.06.03 (Chill Capybar]
[C7x_1 ]      4.223214 s: SCICLIENT: DMSC FW revision 0x8  
[C7x_1 ]      4.223224 s: SCICLIENT: DMSC FW ABI revision 3.1
[C7x_1 ]      4.223235 s: SCICLIENT: Init ... Done !!!
[C7x_1 ]      4.223243 s: UDMA: Init ... !!!
[C7x_1 ]      4.224893 s: UDMA: Init ... Done !!!
[C7x_1 ]      4.224906 s: MEM: Init ... !!!
[C7x_1 ]      4.224917 s: MEM: Created heap (DDR_LOCAL_MEM, id=0, flags=0x00000004) @ 117000000 of size 268435456 bytes !!!
[C7x_1 ]      4.224936 s: MEM: Created heap (L3_MEM, id=1, flags=0x00000001) @ 70020000 of size 8159232 bytes !!!
[C7x_1 ]      4.224954 s: MEM: Created heap (L2_MEM, id=2, flags=0x00000001) @ 64800000 of size 458752 bytes !!!
[C7x_1 ]      4.224971 s: MEM: Created heap (L1_MEM, id=3, flags=0x00000001) @ 64e00000 of size 16384 bytes !!!
[C7x_1 ]      4.224987 s: MEM: Created heap (DDR_SCRATCH_MEM, id=4, flags=0x00000001) @ 100000000 of size 385875968 bytes !!!
[C7x_1 ]      4.225006 s: MEM: Init ... Done !!!
[C7x_1 ]      4.225014 s: IPC: Init ... !!!
[C7x_1 ]      4.225028 s: IPC: 8 CPUs participating in IPC !!!
[C7x_1 ]      4.225041 s: IPC: Waiting for HLOS to be ready ... !!!
[C7x_1 ]     13.475689 s: IPC: HLOS is ready !!!
[C7x_1 ]     13.478044 s: IPC: Init ... Done !!!
[C7x_1 ]     13.478059 s: APP: Syncing with 7 CPUs ... !!!
[C7x_1 ]     14.227415 s: APP: Syncing with 7 CPUs ... Done !!!
[C7x_1 ]     14.227432 s: REMOTE_SERVICE: Init ... !!!
[C7x_1 ]     14.227598 s: REMOTE_SERVICE: Init ... Done !!!
[C7x_1 ]     14.227619 s:  VX_ZONE_INIT:Enabled
[C7x_1 ]     14.227631 s:  VX_ZONE_ERROR:Enabled
[C7x_1 ]     14.227641 s:  VX_ZONE_WARNING:Enabled
[C7x_1 ]     14.227812 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-1 
[C7x_1 ]     14.227880 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-1_PRI_2 
[C7x_1 ]     14.227985 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-1_PRI_3 
[C7x_1 ]     14.228084 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-1_PRI_4 
[C7x_1 ]     14.228202 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-1_PRI_5 
[C7x_1 ]     14.228288 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-1_PRI_6 
[C7x_1 ]     14.228399 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-1_PRI_7 
[C7x_1 ]     14.228475 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-1_PRI_8 
[C7x_1 ]     14.228497 s:  VX_ZONE_INIT:[tivxInitLocal:130] Initialization Done !!!
[C7x_1 ]     14.228510 s: APP: OpenVX Target kernel init ... !!!
[C7x_1 ]     14.228654 s: APP: OpenVX Target kernel init ... Done !!!
[C7x_1 ]     14.228669 s: APP: Init ... Done !!!
[C7x_1 ]     14.228679 s: APP: Run ... !!!
[C7x_1 ]     14.228687 s: IPC: Starting echo test ...
[C7x_1 ]     14.228939 s: APP: Run ... Done !!!
[C7x_1 ]     14.235544 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[.] mcu3_1[.] C66X_1[P] C66X_2[x] C7X_1[s] 
[C7x_1 ]     14.236010 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[.] C66X_1[P] C66X_2[.] C7X_1[s] 
[C7x_1 ]     14.236051 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[.] C66X_1[P] C66X_2[P] C7X_1[s] 
[C7x_1 ]     14.236113 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[P] C66X_1[P] C66X_2[P] C7X_1[s] 
[C7x_1 ]     14.251334 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[P] mcu3_0[P] mcu3_1[P] C66X_1[P] C66X_2[P] C7X_1[s] 
[C7x_1 ]     14.501594 s: IPC: Echo status: mpu1_0[x] mcu2_0[P] mcu2_1[P] mcu3_0[P] mcu3_1[P] C66X_1[P] C66X_2[P] C7X_1[s] 
[MCU2_0]     53.564871 s: EnetPhy_enableState: PHY 17: no supported caps found
[MCU2_0]     53.565127 s: EnetPhy_enableState: PHY 18: no supported caps found
[MCU2_0]     53.565473 s: EnetPhy_enableState: PHY 19: no supported caps found
[MCU2_0]     53.565753 s: EnetPhy_enableState: PHY 15: no supported caps found
[MCU2_0]     53.663686 s: EnetPhy_enableState: PHY 12: no supported caps found
[MCU2_0]     53.663968 s: EnetPhy_enableState: PHY 16: no supported caps found
[MCU2_0]     53.664231 s: EnetPhy_enableState: PHY 0: no supported caps found
[MCU2_0]     53.664607 s: EnetPhy_enableState: PHY 3: no supported caps found
[MCU2_0]     53.664880 s: EnetPhy_enableState: PHY 17: no supported caps found
[MCU2_0]     53.665144 s: EnetPhy_enableState: PHY 18: no supported caps found
[MCU2_0]     53.665500 s: EnetPhy_enableState: PHY 19: no supported caps found
[MCU2_0]     53.665775 s: EnetPhy_enableState: PHY 15: no supported caps found
[MCU2_0]     53.763688 s: EnetPhy_enableState: PHY 12: no supported caps found
[MCU2_0]     53.763973 s: EnetPhy_enableState: PHY 16: no supported caps found

   We have patched the patch 0001-mcm-Fix-race-condition-in-MCM-request-response-handl_SDK_8_6.patch.

   Could you give us some advices?

Best Regards,

Zhang

Hi, 

davied zhang said:

Now we found after we add application on MCU Domain the phy15 can't found and phy0 is not alive

This could be due to pinmux conflict. 

Can you please share pinmux used in mcu application? Also co form phy0 connected on port-3 of cpsw9g? 

davied zhang said:

   Can CPSW9G be used with the other switch

Yes, you can connect other switch to CPSW9G. 

Best Regards, 

Sudheer

Hi,

    Thanks for your support.

Doredla Sudheer Kumar said:

Also co form phy0 connected on port-3 of cpsw9g? 

    We found phy0 connected on port-8 of cpsw9g, phy15 connected on port-3 of cpsw9g. And we using port-3, the error occurs in PHY0.

   The file J721E_pinmux_data.c we used as follows:

/**
* Note: This file was auto-generated by TI PinMux on 5/10/2019 at 3:40:37 PM.
*
* \file  J721E_pinmux_data.c
*
* \brief  This file contains the pin mux configurations for the boards.
*         These are prepared based on how the peripherals are extended on
*         the boards.
*
* \copyright Copyright (CU) 2019 Texas Instruments Incorporated -
*             http://www.ti.com/
*/

/* ========================================================================== */
/*                             Include Files                                  */
/* ========================================================================== */

#include "J721E_pinmux.h"

/** Peripheral Pin Configurations */


static pinmuxPerCfg_t gDebugss0PinCfg[] =
{
    /* MyDEBUG1 -> TDI -> V1 */
    {
        PIN_TDI, PIN_MODE(0) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyDEBUG1 -> TDO -> V3 */
    {
        PIN_TDO, PIN_MODE(0) | \
        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
    },
    /* MyDEBUG1 -> TMS -> V2 */
    {
        PIN_TMS, PIN_MODE(0) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    {PINMUX_END}
};

static pinmuxModuleCfg_t gDebugssPinCfg[] =
{
    {0, TRUE, gDebugss0PinCfg},
    {PINMUX_END}
};


static pinmuxPerCfg_t gDp0PinCfg[] =
{
    /* MyDP0 -> DP0_HPD -> Y4 */
    {
        PIN_SPI0_CS1, PIN_MODE(5) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    {PINMUX_END}
};

static pinmuxModuleCfg_t gDpPinCfg[] =
{
    {0, TRUE, gDp0PinCfg},
    {PINMUX_END}
};


static pinmuxPerCfg_t gGpio0PinCfg[] =
{
    /* MySYSTEM1 -> GPIO0_0 -> AC18 */
    {
        PIN_EXTINTN, PIN_MODE(7) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyGPIO0 -> GPIO0_97 -> Y28 */
    {
        PIN_RGMII6_TX_CTL, PIN_MODE(7) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyGPIO0 -> GPIO0_98 -> V23 */
    {
        PIN_RGMII6_RX_CTL, PIN_MODE(7) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyGPIO0 -> GPIO0_117 -> W4 */
    {
        PIN_SPI1_CS1, PIN_MODE(7) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyGPIO0 -> GPIO0_127 -> AC4 */
    {
        PIN_UART1_CTSN, PIN_MODE(7) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    {PINMUX_END}
};

static pinmuxPerCfg_t gGpio1PinCfg[] =
{
    /* MyGPIO1 -> GPIO1_0 -> AD5 */
    {
        PIN_UART1_RTSN, PIN_MODE(7) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyGPIO1 -> GPIO1_3 -> W3 */
    {
        PIN_MCAN1_RX, PIN_MODE(7) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyGPIO1 -> GPIO1_5 -> W2 */
    {
        PIN_I3C0_SCL, PIN_MODE(7) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyGPIO1 -> GPIO1_6 -> W1 */
    {
        PIN_I3C0_SDA, PIN_MODE(7) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyGPIO1 -> GPIO1_11 -> U2 */
    {
        PIN_ECAP0_IN_APWM_OUT, PIN_MODE(7) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyGPIO1 -> GPIO1_12 -> U3 */
    {
        PIN_EXT_REFCLK1, PIN_MODE(7) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyGPIO1 -> GPIO1_22 -> R28 */
    {
        PIN_MMC1_SDWP, PIN_MODE(7) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyGPIO1 -> GPIO1_23 -> T28 */
    {
        PIN_MMC2_DAT3, PIN_MODE(7) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyGPIO1 -> GPIO1_24 -> T29 */
    {
        PIN_MMC2_DAT2, PIN_MODE(7) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyGPIO1 -> GPIO1_25 -> T27 */
    {
        PIN_MMC2_DAT1, PIN_MODE(7) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyGPIO1 -> GPIO1_26 -> T24 */
    {
        PIN_MMC2_DAT0, PIN_MODE(7) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    {PINMUX_END}
};

static pinmuxModuleCfg_t gGpioPinCfg[] =
{
    {0, TRUE, gGpio0PinCfg},
    {1, TRUE, gGpio1PinCfg},
    {PINMUX_END}
};


static pinmuxPerCfg_t gI2c2PinCfg[] =
{
    /* MyI2C2 -> I2C2_SCL -> AA1 */
    {
        PIN_SPI0_CLK, PIN_MODE(2) | \
        ((PIN_PULL_DIRECTION | PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE))
    },
    /* MyI2C2 -> I2C2_SDA -> AB5 */
    {
        PIN_SPI0_D0, PIN_MODE(2) | \
        ((PIN_PULL_DIRECTION | PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE))
    },
    {PINMUX_END}
};

static pinmuxPerCfg_t gI2c6PinCfg[] =
{
    /* MyI2C6 -> I2C6_SCL -> AA3 */
    {
        PIN_SPI0_D1, PIN_MODE(2) | \
        ((PIN_PULL_DIRECTION | PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE))
    },
    /* MyI2C6 -> I2C6_SDA -> Y2 */
    {
        PIN_SPI1_D1, PIN_MODE(2) | \
        ((PIN_PULL_DIRECTION | PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE))
    },
    {PINMUX_END}
};

static pinmuxPerCfg_t gI2c0PinCfg[] =
{
    /* MyI2C0 -> I2C0_SCL -> AC5 */
    {
        PIN_I2C0_SCL, PIN_MODE(0) | \
        ((PIN_PULL_DIRECTION | PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE))
    },
    /* MyI2C0 -> I2C0_SDA -> AA5 */
    {
        PIN_I2C0_SDA, PIN_MODE(0) | \
        ((PIN_PULL_DIRECTION | PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE))
    },
    {PINMUX_END}
};

static pinmuxPerCfg_t gI2c1PinCfg[] =
{
    /* MyI2C1 -> I2C1_SCL -> Y6 */
    {
        PIN_I2C1_SCL, PIN_MODE(0) | \
        ((PIN_PULL_DIRECTION | PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE))
    },
    /* MyI2C1 -> I2C1_SDA -> AA6 */
    {
        PIN_I2C1_SDA, PIN_MODE(0) | \
        ((PIN_PULL_DIRECTION | PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE))
    },
    {PINMUX_END}
};

static pinmuxPerCfg_t gI2c3PinCfg[] =
{
    /* MyI2C3 -> I2C3_SCL -> T26 */
    {
        PIN_MMC2_CLK, PIN_MODE(4) | \
        ((PIN_PULL_DIRECTION | PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE))
    },
    /* MyI2C3 -> I2C3_SDA -> T25 */
    {
        PIN_MMC2_CMD, PIN_MODE(4) | \
        ((PIN_PULL_DIRECTION | PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE))
    },
    {PINMUX_END}
};

static pinmuxModuleCfg_t gI2cPinCfg[] =
{
    {2, TRUE, gI2c2PinCfg},
    {6, TRUE, gI2c6PinCfg},
    {0, TRUE, gI2c0PinCfg},
    {1, TRUE, gI2c1PinCfg},
    {3, TRUE, gI2c3PinCfg},
    {PINMUX_END}
};


static pinmuxPerCfg_t gMcan2PinCfg[] =
{
    /* MyMCAN2 -> MCAN2_RX -> AC2 */
    {
        PIN_UART0_CTSN, PIN_MODE(3) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyMCAN2 -> MCAN2_TX -> AB1 */
    {
        PIN_UART0_RTSN, PIN_MODE(3) | \
        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
    },
    {PINMUX_END}
};

static pinmuxPerCfg_t gMcan0PinCfg[] =
{
    /* MyMCAN0 -> MCAN0_RX -> W5 */
    {
        PIN_MCAN0_RX, PIN_MODE(0) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyMCAN0 -> MCAN0_TX -> W6 */
    {
        PIN_MCAN0_TX, PIN_MODE(0) | \
        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
    },
    {PINMUX_END}
};

static pinmuxModuleCfg_t gMcanPinCfg[] =
{
    // {2, TRUE, gMcan2PinCfg},
    // {0, TRUE, gMcan0PinCfg},
    {PINMUX_END}
};


static pinmuxPerCfg_t gMcu_i2c0PinCfg[] =
{
    /* MyMCU_I2C0 -> MCU_I2C0_SCL -> J26 */
    {
        PIN_MCU_I2C0_SCL, PIN_MODE(0) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyMCU_I2C0 -> MCU_I2C0_SDA -> H25 */
    {
        PIN_MCU_I2C0_SDA, PIN_MODE(0) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    {PINMUX_END}
};

static pinmuxModuleCfg_t gMcu_i2cPinCfg[] =
{
    {0, TRUE, gMcu_i2c0PinCfg},
    {PINMUX_END}
};


static pinmuxPerCfg_t gMcu_i3c0PinCfg[] =
{
    /* MyMCU_I3C0 -> MCU_I3C0_SCL -> D26 */
    {
        PIN_MCU_I3C0_SCL, PIN_MODE(0) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyMCU_I3C0 -> MCU_I3C0_SDA -> D25 */
    {
        PIN_MCU_I3C0_SDA, PIN_MODE(0) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyMCU_I3C0 -> MCU_I3C0_SDAPULLEN -> E26 */
    {
        PIN_PMIC_POWER_EN0, PIN_MODE(0) | \
        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
    },
    {PINMUX_END}
};

static pinmuxModuleCfg_t gMcu_i3cPinCfg[] =
{
    {0, TRUE, gMcu_i3c0PinCfg},
    {PINMUX_END}
};


static pinmuxPerCfg_t gMcu_mcan0PinCfg[] =
{
    /* MyMCU_MCAN0 -> MCU_MCAN0_RX -> C29 */
    {
        PIN_MCU_MCAN0_RX, PIN_MODE(0) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyMCU_MCAN0 -> MCU_MCAN0_TX -> D29 */
    {
        PIN_MCU_MCAN0_TX, PIN_MODE(0) | \
        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
    },
    {PINMUX_END}
};

static pinmuxPerCfg_t gMcu_mcan1PinCfg[] =
{
    /* MyMCU_MCAN1 -> MCU_MCAN1_RX -> G24 */
    {
        PIN_WKUP_GPIO0_5, PIN_MODE(0) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyMCU_MCAN1 -> MCU_MCAN1_TX -> G25 */
    {
        PIN_WKUP_GPIO0_4, PIN_MODE(0) | \
        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
    },
    {PINMUX_END}
};

static pinmuxModuleCfg_t gMcu_mcanPinCfg[] =
{
    {0, TRUE, gMcu_mcan0PinCfg},
    {1, TRUE, gMcu_mcan1PinCfg},
    {PINMUX_END}
};


static pinmuxPerCfg_t gMcu_mdio0PinCfg[] =
{
    /* MyMCU_MDIO1 -> MCU_MDIO0_MDC -> F23 */
    {
        PIN_MCU_MDIO0_MDC, PIN_MODE(7) | \
        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
    },
    /* MyMCU_MDIO1 -> MCU_MDIO0_MDIO -> E23 */
    {
        PIN_MCU_MDIO0_MDIO, PIN_MODE(0) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    {PINMUX_END}
};

static pinmuxModuleCfg_t gMcu_mdioPinCfg[] =
{
    {0, TRUE, gMcu_mdio0PinCfg},
    {PINMUX_END}
};


static pinmuxPerCfg_t gMcu_fss0_ospi0PinCfg[] =
{
    /* MyMCU_OSPI0 -> MCU_OSPI0_CLK -> E20 */
    {
        PIN_MCU_OSPI0_CLK, PIN_MODE(0) | \
        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
    },
    /* MyMCU_OSPI0 -> MCU_OSPI0_CSn0 -> F19 */
    {
        PIN_MCU_OSPI0_CSN0, PIN_MODE(0) | \
        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
    },
    /* MyMCU_OSPI0 -> MCU_OSPI0_D0 -> D20 */
    {
        PIN_MCU_OSPI0_D0, PIN_MODE(0) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyMCU_OSPI0 -> MCU_OSPI0_D1 -> G19 */
    {
        PIN_MCU_OSPI0_D1, PIN_MODE(0) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyMCU_OSPI0 -> MCU_OSPI0_D2 -> G20 */
    {
        PIN_MCU_OSPI0_D2, PIN_MODE(0) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyMCU_OSPI0 -> MCU_OSPI0_D3 -> F20 */
    {
        PIN_MCU_OSPI0_D3, PIN_MODE(0) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyMCU_OSPI0 -> MCU_OSPI0_D4 -> F21 */
    {
        PIN_MCU_OSPI0_D4, PIN_MODE(0) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyMCU_OSPI0 -> MCU_OSPI0_D5 -> E21 */
    {
        PIN_MCU_OSPI0_D5, PIN_MODE(0) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyMCU_OSPI0 -> MCU_OSPI0_D6 -> B22 */
    {
        PIN_MCU_OSPI0_D6, PIN_MODE(0) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyMCU_OSPI0 -> MCU_OSPI0_D7 -> G21 */
    {
        PIN_MCU_OSPI0_D7, PIN_MODE(0) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyMCU_OSPI0 -> MCU_OSPI0_DQS -> D21 */
    {
        PIN_MCU_OSPI0_DQS, PIN_MODE(0) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    {PINMUX_END}
};

static pinmuxPerCfg_t gMcu_fss0_ospi1PinCfg[] =
{
    /* MyMCU_OSPI1 -> MCU_OSPI1_CLK -> F22 */
    {
        PIN_MCU_OSPI1_CLK, PIN_MODE(0) | \
        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
    },
    /* MyMCU_OSPI1 -> MCU_OSPI1_CSn0 -> C22 */
    {
        PIN_MCU_OSPI1_CSN0, PIN_MODE(0) | \
        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
    },
    /* MyMCU_OSPI1 -> MCU_OSPI1_D0 -> D22 */
    {
        PIN_MCU_OSPI1_D0, PIN_MODE(0) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyMCU_OSPI1 -> MCU_OSPI1_D1 -> G22 */
    {
        PIN_MCU_OSPI1_D1, PIN_MODE(0) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyMCU_OSPI1 -> MCU_OSPI1_D2 -> D23 */
    {
        PIN_MCU_OSPI1_D2, PIN_MODE(0) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyMCU_OSPI1 -> MCU_OSPI1_D3 -> C23 */
    {
        PIN_MCU_OSPI1_D3, PIN_MODE(0) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyMCU_OSPI1 -> MCU_OSPI1_DQS -> B23 */
    {
        PIN_MCU_OSPI1_DQS, PIN_MODE(0) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyMCU_OSPI1 -> MCU_OSPI1_LBCLKO -> A23 */
    {
        PIN_MCU_OSPI1_LBCLKO, PIN_MODE(0) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    {PINMUX_END}
};

static pinmuxModuleCfg_t gMcu_fss0_ospiPinCfg[] =
{
    {0, TRUE, gMcu_fss0_ospi0PinCfg},
    {1, TRUE, gMcu_fss0_ospi1PinCfg},
    {PINMUX_END}
};

static pinmuxPerCfg_t gMcu_fss0_hpb0PinCfg[] =
{
    /* MyMCU_FSS0_HPB1 -> MCU_HYPERBUS0_CK -> E20 */
    {
        PIN_MCU_OSPI0_CLK, PIN_MODE(1) | \
        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
    },
    /* MyMCU_FSS0_HPB1 -> MCU_HYPERBUS0_CSn0 -> F19 */
    {
        PIN_MCU_OSPI0_CSN0, PIN_MODE(1) | \
        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
    },
    /* MyMCU_FSS0_HPB1 -> MCU_HYPERBUS0_DQ0 -> D20 */
    {
        PIN_MCU_OSPI0_D0, PIN_MODE(1) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyMCU_FSS0_HPB1 -> MCU_HYPERBUS0_DQ1 -> G19 */
    {
        PIN_MCU_OSPI0_D1, PIN_MODE(1) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyMCU_FSS0_HPB1 -> MCU_HYPERBUS0_DQ2 -> G20 */
    {
        PIN_MCU_OSPI0_D2, PIN_MODE(1) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyMCU_FSS0_HPB1 -> MCU_HYPERBUS0_DQ3 -> F20 */
    {
        PIN_MCU_OSPI0_D3, PIN_MODE(1) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyMCU_FSS0_HPB1 -> MCU_HYPERBUS0_DQ4 -> F21 */
    {
        PIN_MCU_OSPI0_D4, PIN_MODE(1) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyMCU_FSS0_HPB1 -> MCU_HYPERBUS0_DQ5 -> E21 */
    {
        PIN_MCU_OSPI0_D5, PIN_MODE(1) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyMCU_FSS0_HPB1 -> MCU_HYPERBUS0_DQ6 -> B22 */
    {
        PIN_MCU_OSPI0_D6, PIN_MODE(1) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyMCU_FSS0_HPB1 -> MCU_HYPERBUS0_DQ7 -> G21 */
    {
        PIN_MCU_OSPI0_D7, PIN_MODE(1) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyMCU_FSS0_HPB1 -> MCU_OSPI0_DQS -> D21 */
    {
        PIN_MCU_OSPI0_DQS, PIN_MODE(1) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyMCU_FSS0_HPB1 -> MCU_OSPI0_LBCLKO -> C21 */
    {
        PIN_MCU_OSPI0_LBCLKO, PIN_MODE(1) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    {PINMUX_END}
};

static pinmuxModuleCfg_t gMcu_fss0_hpbPinCfg[] =
{
    {0, TRUE, gMcu_fss0_hpb0PinCfg},
    {PINMUX_END}
};


static pinmuxPerCfg_t gMcu_rgmii1PinCfg[] =
{
    /* MyMCU_RGMII1 -> MCU_RGMII1_RD0 -> B24 */
    {
        PIN_MCU_RGMII1_RD0, PIN_MODE(7) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyMCU_RGMII1 -> MCU_RGMII1_RD1 -> A24 */
    {
        PIN_MCU_RGMII1_RD1, PIN_MODE(7) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyMCU_RGMII1 -> MCU_RGMII1_RD2 -> D24 */
    {
        PIN_MCU_RGMII1_RD2, PIN_MODE(0) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyMCU_RGMII1 -> MCU_RGMII1_RD3 -> A25 */
    {
        PIN_MCU_RGMII1_RD3, PIN_MODE(0) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyMCU_RGMII1 -> MCU_RGMII1_RXC -> C24 */
    {
        PIN_MCU_RGMII1_RXC, PIN_MODE(7) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyMCU_RGMII1 -> MCU_RGMII1_RX_CTL -> C25 */
    {
        PIN_MCU_RGMII1_RX_CTL, PIN_MODE(7) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyMCU_RGMII1 -> MCU_RGMII1_TD0 -> B25 */
    {
        PIN_MCU_RGMII1_TD0, PIN_MODE(0) | \
        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
    },
    /* MyMCU_RGMII1 -> MCU_RGMII1_TD1 -> A26 */
    {
        PIN_MCU_RGMII1_TD1, PIN_MODE(0) | \
        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
    },
    /* MyMCU_RGMII1 -> MCU_RGMII1_TD2 -> A27 */
    {
        PIN_MCU_RGMII1_TD2, PIN_MODE(0) | \
        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
    },
    /* MyMCU_RGMII1 -> MCU_RGMII1_TD3 -> A28 */
    {
        PIN_MCU_RGMII1_TD3, PIN_MODE(0) | \
        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
    },
    /* MyMCU_RGMII1 -> MCU_RGMII1_TXC -> B26 */
    {
        PIN_MCU_RGMII1_TXC, PIN_MODE(0) | \
        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
    },
    /* MyMCU_RGMII1 -> MCU_RGMII1_TX_CTL -> B27 */
    {
        PIN_MCU_RGMII1_TX_CTL, PIN_MODE(0) | \
        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
    },
    {PINMUX_END}
};

static pinmuxModuleCfg_t gMcu_rgmiiPinCfg[] =
{
    {1, TRUE, gMcu_rgmii1PinCfg},
    {PINMUX_END}
};


static pinmuxPerCfg_t gMcu_uart0PinCfg[] =
{
    /* MyMCU_UART0 -> MCU_UART0_CTSn -> H29 */
    {
        PIN_WKUP_GPIO0_14, PIN_MODE(0) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyMCU_UART0 -> MCU_UART0_RTSn -> J27 */
    {
        PIN_WKUP_GPIO0_15, PIN_MODE(0) | \
        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
    },
    /* MyMCU_UART0 -> MCU_UART0_RXD -> H28 */
    {
        PIN_WKUP_GPIO0_13, PIN_MODE(0) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyMCU_UART0 -> MCU_UART0_TXD -> G29 */
    {
        PIN_WKUP_GPIO0_12, PIN_MODE(0) | \
        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
    },
    {PINMUX_END}
};

static pinmuxModuleCfg_t gMcu_uartPinCfg[] =
{
    {0, TRUE, gMcu_uart0PinCfg},
    {PINMUX_END}
};


static pinmuxPerCfg_t gMdio0PinCfg[] =
{
    /* MyMDIO1 -> MDIO0_MDC -> V24 */
    {
        PIN_MDIO0_MDC, PIN_MODE(0) | \
        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
    },
    /* MyMDIO1 -> MDIO0_MDIO -> V26 */
    {
        PIN_MDIO0_MDIO, PIN_MODE(0) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    {PINMUX_END}
};

static pinmuxModuleCfg_t gMdioPinCfg[] =
{
    {0, TRUE, gMdio0PinCfg},
    {PINMUX_END}
};


static pinmuxPerCfg_t gMlb0PinCfg[] =
{
    /* MyMLB0 -> MLB0_MLBCN -> AE2 */
    {
        PIN_MLB0_MLBCN, PIN_MODE(0) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyMLB0 -> MLB0_MLBCP -> AD2 */
    {
        PIN_MLB0_MLBCP, PIN_MODE(0) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyMLB0 -> MLB0_MLBDN -> AD3 */
    {
        PIN_MLB0_MLBDN, PIN_MODE(0) | \
        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
    },
    /* MyMLB0 -> MLB0_MLBDP -> AC3 */
    {
        PIN_MLB0_MLBDP, PIN_MODE(0) | \
        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
    },
    /* MyMLB0 -> MLB0_MLBSN -> AC1 */
    {
        PIN_MLB0_MLBSN, PIN_MODE(0) | \
        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
    },
    /* MyMLB0 -> MLB0_MLBSP -> AD1 */
    {
        PIN_MLB0_MLBSP, PIN_MODE(0) | \
        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
    },
    {PINMUX_END}
};

static pinmuxModuleCfg_t gMlbPinCfg[] =
{
    {0, TRUE, gMlb0PinCfg},
    {PINMUX_END}
};


static pinmuxPerCfg_t gMmcsd1PinCfg[] =
{
    /* MyMMC1 -> MMC1_CLK -> P25 */
    {
        PIN_MMC1_CLK, PIN_MODE(0) | \
        ((PIN_PULL_DIRECTION | PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE))
    },
    /* MyMMC1 -> MMC1_CMD -> R29 */
    {
        PIN_MMC1_CMD, PIN_MODE(0) | \
        ((PIN_PULL_DIRECTION | PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE))
    },
    /* MyMMC1 -> MMC1_DAT0 -> R24 */
    {
        PIN_MMC1_DAT0, PIN_MODE(0) | \
        ((PIN_PULL_DIRECTION | PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE))
    },
    /* MyMMC1 -> MMC1_DAT1 -> P24 */
    {
        PIN_MMC1_DAT1, PIN_MODE(0) | \
        ((PIN_PULL_DIRECTION | PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE))
    },
    /* MyMMC1 -> MMC1_DAT2 -> R25 */
    {
        PIN_MMC1_DAT2, PIN_MODE(0) | \
        ((PIN_PULL_DIRECTION | PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE))
    },
    /* MyMMC1 -> MMC1_DAT3 -> R26 */
    {
        PIN_MMC1_DAT3, PIN_MODE(0) | \
        ((PIN_PULL_DIRECTION | PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE))
    },
    /* MyMMC1 -> MMC1_SDCD -> P23 */
    {
        PIN_MMC1_SDCD, PIN_MODE(0) | \
        ((PIN_PULL_DIRECTION | PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE))
    },
    /* MyMMC1 -> MMC1_CLKLB */
    {
        PIN_MMC1_CLKLB, PIN_MODE(0) | \
        ((PIN_PULL_DIRECTION | PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE))
    },
    {PINMUX_END}
};

static pinmuxModuleCfg_t gMmcsdPinCfg[] =
{
    {1, TRUE, gMmcsd1PinCfg},
    {PINMUX_END}
};


static pinmuxPerCfg_t gSystem0PinCfg[] =
{
    /* MySYSTEM1 -> AUDIO_EXT_REFCLK2 -> W26 */
    {
        PIN_RGMII6_RXC, PIN_MODE(3) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MySYSTEM1 -> OBSCLK0 -> V5 */
    {
        PIN_TIMER_IO1, PIN_MODE(2) | \
        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
    },
    /* MySYSTEM1 -> PORz_OUT -> U1 */
    {
        PIN_PORZ_OUT, PIN_MODE(0) | \
        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
    },
    /* MySYSTEM1 -> RESETSTATz -> T6 */
    {
        PIN_RESETSTATZ, PIN_MODE(0) | \
        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
    },
    /* MySYSTEM1 -> SOC_SAFETY_ERRORn -> U4 */
    {
        PIN_SOC_SAFETY_ERRORN, PIN_MODE(0) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MySYSTEM1 -> SYSCLKOUT0 -> V6 */
    {
        PIN_TIMER_IO0, PIN_MODE(2) | \
        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
    },
    {PINMUX_END}
};

static pinmuxModuleCfg_t gSystemPinCfg[] =
{
    {0, TRUE, gSystem0PinCfg},
    {PINMUX_END}
};


static pinmuxPerCfg_t gUart4PinCfg[] =
{
    /* MyUART4 -> UART4_RXD -> W23 */
    {
        PIN_RGMII6_TD3, PIN_MODE(1) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyUART4 -> UART4_TXD -> W28 */
    {
        PIN_RGMII6_TD2, PIN_MODE(1) | \
        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
    },
    {PINMUX_END}
};

static pinmuxPerCfg_t gUart0PinCfg[] =
{
    /* MyUART0 -> UART0_CTSn -> Y3 */
    {
        PIN_SPI1_CS0, PIN_MODE(1) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyUART0 -> UART0_RTSn -> AA2 */
    {
        PIN_SPI0_CS0, PIN_MODE(1) | \
        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
    },
    /* MyUART0 -> UART0_RXD -> AB2 */
    {
        PIN_UART0_RXD, PIN_MODE(0) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyUART0 -> UART0_TXD -> AB3 */
    {
        PIN_UART0_TXD, PIN_MODE(0) | \
        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
    },
    {PINMUX_END}
};

static pinmuxPerCfg_t gUart2PinCfg[] =
{
    /* MyUART2 -> UART2_RXD -> Y1 */
    {
        PIN_SPI1_CLK, PIN_MODE(3) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyUART2 -> UART2_TXD -> Y5 */
    {
        PIN_SPI1_D0, PIN_MODE(3) | \
        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
    },
    {PINMUX_END}
};

static pinmuxPerCfg_t gUart1PinCfg[] =
{
    /* MyUART1 -> UART1_RXD -> AA4 */
    {
        PIN_UART1_RXD, PIN_MODE(0) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyUART1 -> UART1_TXD -> AB4 */
    {
        PIN_UART1_TXD, PIN_MODE(0) | \
        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
    },
    {PINMUX_END}
};

static pinmuxModuleCfg_t gUartPinCfg[] =
{
    {4, TRUE, gUart4PinCfg},
    {0, TRUE, gUart0PinCfg},
    {2, TRUE, gUart2PinCfg},
    {1, TRUE, gUart1PinCfg},
    {PINMUX_END}
};


static pinmuxPerCfg_t gUsb1PinCfg[] =
{
    /* MyUSB1 -> USB1_DRVVBUS -> V4 */
    {
        PIN_MCAN1_TX, PIN_MODE(4) | \
        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
    },
    {PINMUX_END}
};

static pinmuxPerCfg_t gUsb0PinCfg[] =
{
    /* MyUSB0 -> USB0_DRVVBUS -> U6 */
    {
        PIN_USB0_DRVVBUS, PIN_MODE(0) | \
        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
    },
    {PINMUX_END}
};

static pinmuxModuleCfg_t gUsbPinCfg[] =
{
    {1, TRUE, gUsb1PinCfg},
    {0, TRUE, gUsb0PinCfg},
    {PINMUX_END}
};


static pinmuxPerCfg_t gWkup_debugss0PinCfg[] =
{
    /* MyWKUP_DEBUG -> EMU0 -> C26 */
    {
        PIN_EMU0, PIN_MODE(0) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyWKUP_DEBUG -> EMU1 -> B29 */
    {
        PIN_EMU1, PIN_MODE(0) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyWKUP_DEBUG -> TCK -> E29 */
    {
        PIN_TCK, PIN_MODE(0) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyWKUP_DEBUG -> TRSTn -> F24 */
    {
        PIN_TRSTN, PIN_MODE(0) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    {PINMUX_END}
};

static pinmuxModuleCfg_t gWkup_debugssPinCfg[] =
{
    {0, TRUE, gWkup_debugss0PinCfg},
    {PINMUX_END}
};


static pinmuxPerCfg_t gWkup_gpio0PinCfg[] =
{
    /* MyWKUP_GPIO0 -> WKUP_GPIO0_0 -> F26 */
    {
        PIN_WKUP_GPIO0_0, PIN_MODE(7) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyWKUP_GPIO0 -> WKUP_GPIO0_1 -> F25 */
    {
        PIN_WKUP_GPIO0_1, PIN_MODE(7) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyWKUP_GPIO0 -> WKUP_GPIO0_2 -> F28 */
    {
        PIN_WKUP_GPIO0_2, PIN_MODE(7) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyWKUP_GPIO0 -> WKUP_GPIO0_3 -> F27 */
    {
        PIN_WKUP_GPIO0_3, PIN_MODE(7) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyWKUP_GPIO0 -> WKUP_GPIO0_6 -> F29 */
    {
        PIN_WKUP_GPIO0_6, PIN_MODE(7) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyWKUP_GPIO0 -> WKUP_GPIO0_7 -> G28 */
    {
        PIN_WKUP_GPIO0_7, PIN_MODE(3) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyWKUP_GPIO0 -> WKUP_GPIO0_8 -> G27 */
    {
        PIN_WKUP_GPIO0_8, PIN_MODE(0) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyWKUP_GPIO0 -> WKUP_GPIO0_9 -> G26 */
    {
        PIN_WKUP_GPIO0_9, PIN_MODE(7) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyWKUP_GPIO0 -> WKUP_GPIO0_17 -> C21 */
    {
        PIN_MCU_OSPI0_LBCLKO, PIN_MODE(7) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyWKUP_GPIO0 -> WKUP_GPIO0_53 -> E24 */
    {
        PIN_MCU_SPI0_D0, PIN_MODE(7) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyWKUP_GPIO0 -> WKUP_GPIO0_54 -> E28 */
    {
        PIN_MCU_SPI0_D1, PIN_MODE(7) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyWKUP_GPIO0 -> WKUP_GPIO0_55 -> E25 */
    {
        PIN_MCU_SPI0_CS0, PIN_MODE(7) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    {PINMUX_END}
};

static pinmuxModuleCfg_t gWkup_gpioPinCfg[] =
{
    {0, TRUE, gWkup_gpio0PinCfg},
    {PINMUX_END}
};


static pinmuxPerCfg_t gWkup_i2c0PinCfg[] =
{
    /* MyWKUP_I2C0 -> WKUP_I2C0_SCL -> J25 */
    {
        PIN_WKUP_I2C0_SCL, PIN_MODE(0) | \
        ((PIN_PULL_DIRECTION | PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE))
    },
    /* MyWKUP_I2C0 -> WKUP_I2C0_SDA -> H24 */
    {
        PIN_WKUP_I2C0_SDA, PIN_MODE(0) | \
        ((PIN_PULL_DIRECTION | PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE))
    },
    {PINMUX_END}
};

static pinmuxModuleCfg_t gWkup_i2cPinCfg[] =
{
    {0, TRUE, gWkup_i2c0PinCfg},
    {PINMUX_END}
};


static pinmuxPerCfg_t gWkup_system0PinCfg[] =
{
    /* MyWKUP_SYSTEM -> MCU_PORz_OUT -> B28 */
    {
        PIN_MCU_PORZ_OUT, PIN_MODE(0) | \
        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
    },
    /* MyWKUP_SYSTEM -> MCU_RESETSTATz -> C27 */
    {
        PIN_MCU_RESETSTATZ, PIN_MODE(0) | \
        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
    },
    /* MyWKUP_SYSTEM -> MCU_RESETz -> D28 */
    {
        PIN_MCU_RESETZ, PIN_MODE(0) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyWKUP_SYSTEM -> MCU_SAFETY_ERRORn -> D27 */
    {
        PIN_MCU_SAFETY_ERRORN, PIN_MODE(0) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyWKUP_SYSTEM -> PMIC_POWER_EN1 -> G23 */
    {
        PIN_PMIC_POWER_EN1, PIN_MODE(0) | \
        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
    },
    /* MyWKUP_SYSTEM -> PORz -> J24 */
    {
        PIN_PORZ, PIN_MODE(0) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyWKUP_SYSTEM -> RESET_REQz -> C28 */
    {
        PIN_RESET_REQZ, PIN_MODE(0) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    {PINMUX_END}
};

static pinmuxModuleCfg_t gWkup_systemPinCfg[] =
{
    {0, TRUE, gWkup_system0PinCfg},
    {PINMUX_END}
};


static pinmuxPerCfg_t gWkup_uart0PinCfg[] =
{
    /* MyWKUP_UART0 -> WKUP_UART0_RXD -> J29 */
    {
        PIN_WKUP_UART0_RXD, PIN_MODE(0) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyWKUP_UART0 -> WKUP_UART0_TXD -> J28 */
    {
        PIN_WKUP_UART0_TXD, PIN_MODE(0) | \
        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
    },
    {PINMUX_END}
};

static pinmuxModuleCfg_t gWkup_uartPinCfg[] =
{
    {0, TRUE, gWkup_uart0PinCfg},
    {PINMUX_END}
};

static pinmuxPerCfg_t gMcasp2PinCfg[] =
{
    /* MyMCASP2 -> MCASP2_ACLKX -> AA29 */
    {
        PIN_PRG0_PRU1_GPO19, PIN_MODE(12) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyMCASP2 -> MCASP2_AFSX -> AA26 */
    {
        PIN_PRG0_PRU1_GPO18, PIN_MODE(12) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyMCASP2 -> MCASP2_AXR3 -> Y25 */
    {
        PIN_PRG0_PRU1_GPO17, PIN_MODE(12) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    {PINMUX_END}
};

static pinmuxPerCfg_t gMcasp0PinCfg[] =
{
    /* MyMCASP10 -> MCASP10_ACLKX -> U23 */
    {
        PIN_RGMII5_TX_CTL, PIN_MODE(12) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyMCASP10 -> MCASP10_AFSX -> U26 */
    {
        PIN_RGMII5_RX_CTL, PIN_MODE(12) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyMCASP10 -> MCASP10_AXR0 -> V28 */
    {
        PIN_RGMII5_TD3, PIN_MODE(12) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyMCASP10 -> MCASP10_AXR1 -> V29 */
    {
        PIN_RGMII5_TD2, PIN_MODE(12) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyMCASP10 -> MCASP10_AXR2 -> U29 */
    {
        PIN_RGMII5_TXC, PIN_MODE(12) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyMCASP10 -> MCASP10_AXR3 -> U25 */
    {
        PIN_RGMII5_RXC, PIN_MODE(7) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyMCASP10 -> MCASP10_AXR4 -> V25 */
    {
        PIN_RGMII6_TD1, PIN_MODE(12) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyMCASP10 -> MCASP10_AXR5 -> W27 */
    {
        PIN_RGMII6_TD0, PIN_MODE(12) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyMCASP10 -> MCASP10_AXR6 -> W29 */
    {
        PIN_RGMII6_TXC, PIN_MODE(7) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* AUDIO_EXT_REFCLK2 (to PCM3168a) */
    {
        PIN_RGMII6_RXC, PIN_MODE(3) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    {PINMUX_END}
};

static pinmuxPerCfg_t gMcasp1PinCfg[] =
{
    /* MyMCASP11 -> MCASP11_ACLKX -> V27 */
    {
        PIN_RGMII5_TD1, PIN_MODE(12) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyMCASP11 -> MCASP11_AFSX -> U28 */
    {
        PIN_RGMII5_TD0, PIN_MODE(12) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyMCASP11 -> MCASP11_AXR0 -> U27 */
    {
        PIN_RGMII5_RD3, PIN_MODE(7) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyMCASP11 -> MCASP11_AXR1 -> U24 */
    {
        PIN_RGMII5_RD2, PIN_MODE(7) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyMCASP11 -> MCASP11_AXR2 -> R23 */
    {
        PIN_RGMII5_RD1, PIN_MODE(12) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyMCASP11 -> MCASP11_AXR3 -> T23 */
    {
        PIN_RGMII5_RD0, PIN_MODE(12) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyMCASP11 -> MCASP11_AXR4 -> Y29 */
    {
        PIN_RGMII6_RD3, PIN_MODE(12) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyMCASP11 -> MCASP11_AXR5 -> Y27 */
    {
        PIN_RGMII6_RD2, PIN_MODE(12) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyMCASP11 -> MCASP11_AXR6 -> W24 */
    {
        PIN_RGMII6_RD1, PIN_MODE(12) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyMCASP11 -> MCASP11_AXR7 -> W25 */
    {
        PIN_RGMII6_RD0, PIN_MODE(12) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    {PINMUX_END}
};

static pinmuxModuleCfg_t gMcaspPinCfg[] =
{
    {2, TRUE, gMcasp2PinCfg},
    {0, TRUE, gMcasp0PinCfg},
    {1, TRUE, gMcasp1PinCfg},
    {PINMUX_END}
};


static pinmuxPerCfg_t gMcu_adc0PinCfg[] =
{
    /* MyMCU_ADC0 -> MCU_ADC0_AIN0 -> K25 */
    {
        PIN_MCU_ADC0_AIN0, PIN_MODE(0) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyMCU_ADC0 -> MCU_ADC0_AIN1 -> K26 */
    {
        PIN_MCU_ADC0_AIN1, PIN_MODE(0) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyMCU_ADC0 -> MCU_ADC0_AIN2 -> K28 */
    {
        PIN_MCU_ADC0_AIN2, PIN_MODE(0) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyMCU_ADC0 -> MCU_ADC0_AIN3 -> L28 */
    {
        PIN_MCU_ADC0_AIN3, PIN_MODE(0) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyMCU_ADC0 -> MCU_ADC0_AIN4 -> K24 */
    {
        PIN_MCU_ADC0_AIN4, PIN_MODE(0) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyMCU_ADC0 -> MCU_ADC0_AIN5 -> K27 */
    {
        PIN_MCU_ADC0_AIN5, PIN_MODE(0) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyMCU_ADC0 -> MCU_ADC0_AIN6 -> K29 */
    {
        PIN_MCU_ADC0_AIN6, PIN_MODE(0) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyMCU_ADC0 -> MCU_ADC0_AIN7 -> L29 */
    {
        PIN_MCU_ADC0_AIN7, PIN_MODE(0) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    {PINMUX_END}
};
static pinmuxPerCfg_t gMcu_adc1PinCfg[] =
{
    /* MyMCU_ADC1 -> MCU_ADC1_AIN0 -> N23 */
    {
        PIN_MCU_ADC1_AIN0, PIN_MODE(0) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyMCU_ADC1 -> MCU_ADC1_AIN1 -> M25 */
    {
        PIN_MCU_ADC1_AIN1, PIN_MODE(0) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyMCU_ADC1 -> MCU_ADC1_AIN2 -> L24 */
    {
        PIN_MCU_ADC1_AIN2, PIN_MODE(0) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyMCU_ADC1 -> MCU_ADC1_AIN3 -> L26 */
    {
        PIN_MCU_ADC1_AIN3, PIN_MODE(0) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyMCU_ADC1 -> MCU_ADC1_AIN4 -> N24 */
    {
        PIN_MCU_ADC1_AIN4, PIN_MODE(0) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyMCU_ADC1 -> MCU_ADC1_AIN5 -> M24 */
    {
        PIN_MCU_ADC1_AIN5, PIN_MODE(0) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyMCU_ADC1 -> MCU_ADC1_AIN6 -> L25 */
    {
        PIN_MCU_ADC1_AIN6, PIN_MODE(0) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyMCU_ADC1 -> MCU_ADC1_AIN7 -> L27 */
    {
        PIN_MCU_ADC1_AIN7, PIN_MODE(0) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    {PINMUX_END}
};
static pinmuxModuleCfg_t gMcu_adcPinCfg[] =
{
    {1, TRUE, gMcu_adc1PinCfg},
    {0, TRUE, gMcu_adc0PinCfg},
    {PINMUX_END}
};


pinmuxBoardCfg_t gJ721E_MainPinmuxData[] =
{
    {0, gDebugssPinCfg},
    {1, gDpPinCfg},
    {2, gGpioPinCfg},
    {3, gI2cPinCfg},
    {4, gMcanPinCfg},
    {5, gMdioPinCfg},
    {6, gMlbPinCfg},
    {7, gMmcsdPinCfg},
    {8, gSystemPinCfg},
    {9, gUartPinCfg},
    {10, gUsbPinCfg},
    {11, gMcaspPinCfg},
    {PINMUX_END}
};

pinmuxBoardCfg_t gJ721E_WkupPinmuxData[] =
{
    {0, gMcu_i2cPinCfg},
    {1, gMcu_i3cPinCfg},
    {2, gMcu_mcanPinCfg},
    {3, gMcu_mdioPinCfg},
    {4, gMcu_fss0_ospiPinCfg},
    {5, gMcu_rgmiiPinCfg},
    {6, gMcu_uartPinCfg},
    {7, gWkup_debugssPinCfg},
    {8, gWkup_gpioPinCfg},
    {9, gWkup_i2cPinCfg},
    {10, gWkup_systemPinCfg},
    {11, gWkup_uartPinCfg},
    {12, gMcu_adcPinCfg},
    {PINMUX_END}
};

pinmuxBoardCfg_t gJ721E_WkupPinmuxDataHpb[] =
{
    {0, gMcu_fss0_hpbPinCfg},
    {PINMUX_END}
};

   If we want to remove phy0 and phy15 from driver, what should we do?

Best Regards,

Zhang

Hi,

davied zhang said:

    We found phy0 connected on port-8 of cpsw9g, phy15 connected on port-3 of cpsw9g. And we using port-3, the error occurs in PHY0.

   The file J721E_pinmux_data.c we used as follows:

There is no pin config difference between Port-3, Port-8 (RGMII lines) & above PinMux.

Can you please confirm Port-3 & Port-8 are in RGMII interface? If Port-8 is in RMII then it conflict with Mcasp configuration.

Can also share the Pin Mux using for CPSW Ports?

davied zhang said:

 If we want to remove phy0 and phy15 from driver, what should we do?

Disable the Ports connected with phy0 & phy15 from "gEthAppPorts" array in app_remoteswitchcfg_server/mcu2_0/main.c file and recompile the EthFw and use the updated binary.

Bets Regards,
Sudheer

Hi,Sudheer

   Thanks for your support.

Doredla Sudheer Kumar said:

Can you please confirm Port-3 & Port-8 are in RGMII interface?

   We found RGMII interface was setted in three ways.

    a. board-support/linux-5.10.162+gitAUTOINC+76b3e88d56-g76b3e88d56/arch/arm64/boot/dts/ti/k3-j721e-gesi-exp-board.dts

    b. pdk_jacinto_08_06_00_31/packages/ti/board/src/j721e_evm/J721E_pinmux_data_gesi_cpsw9g.c

static pinmuxPerCfg_t gRgmii3PinCfg[] =
{
    /* MyRGMII3 -> RGMII3_RD0 -> AF28 */
    {
        PIN_PRG0_PRU0_GPO0, PIN_MODE(4) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyRGMII3 -> RGMII3_RD1 -> AE28 */
    {
        PIN_PRG0_PRU0_GPO1, PIN_MODE(4) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyRGMII3 -> RGMII3_RD2 -> AE27 */
    {
        PIN_PRG0_PRU0_GPO2, PIN_MODE(4) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyRGMII3 -> RGMII3_RD3 -> AD26 */
    {
        PIN_PRG0_PRU0_GPO3, PIN_MODE(4) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyRGMII3 -> RGMII3_RXC -> AE26 */
    {
        PIN_PRG0_PRU0_GPO6, PIN_MODE(4) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyRGMII3 -> RGMII3_RX_CTL -> AD25 */
    {
        PIN_PRG0_PRU0_GPO4, PIN_MODE(4) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyRGMII3 -> RGMII3_TD0 -> AJ28 */
    {
        PIN_PRG0_PRU0_GPO11, PIN_MODE(4) | \
        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
    },
    /* MyRGMII3 -> RGMII3_TD1 -> AH27 */
    {
        PIN_PRG0_PRU0_GPO12, PIN_MODE(4) | \
        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
    },
    /* MyRGMII3 -> RGMII3_TD2 -> AH29 */
    {
        PIN_PRG0_PRU0_GPO13, PIN_MODE(4) | \
        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
    },
    /* MyRGMII3 -> RGMII3_TD3 -> AG28 */
    {
        PIN_PRG0_PRU0_GPO14, PIN_MODE(4) | \
        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
    },
    /* MyRGMII3 -> RGMII3_TXC -> AH28 */
    {
        PIN_PRG0_PRU0_GPO16, PIN_MODE(4) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyRGMII3 -> RGMII3_TX_CTL -> AG27 */
    {
        PIN_PRG0_PRU0_GPO15, PIN_MODE(4) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    {PINMUX_END}
};

static pinmuxPerCfg_t gRgmii4PinCfg[] =
{
    /* MyRGMII4 -> RGMII4_RD0 -> AE29 */
    {
        PIN_PRG0_PRU1_GPO0, PIN_MODE(4) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyRGMII4 -> RGMII4_RD1 -> AD28 */
    {
        PIN_PRG0_PRU1_GPO1, PIN_MODE(4) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyRGMII4 -> RGMII4_RD2 -> AD27 */
    {
        PIN_PRG0_PRU1_GPO2, PIN_MODE(4) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyRGMII4 -> RGMII4_RD3 -> AC25 */
    {
        PIN_PRG0_PRU1_GPO3, PIN_MODE(4) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyRGMII4 -> RGMII4_RXC -> AC26 */
    {
        PIN_PRG0_PRU1_GPO6, PIN_MODE(4) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyRGMII4 -> RGMII4_RX_CTL -> AD29 */
    {
        PIN_PRG0_PRU1_GPO4, PIN_MODE(4) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyRGMII4 -> RGMII4_TD0 -> AG26 */
    {
        PIN_PRG0_PRU1_GPO11, PIN_MODE(4) | \
        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
    },
    /* MyRGMII4 -> RGMII4_TD1 -> AF27 */
    {
        PIN_PRG0_PRU1_GPO12, PIN_MODE(4) | \
        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
    },
    /* MyRGMII4 -> RGMII4_TD2 -> AF26 */
    {
        PIN_PRG0_PRU1_GPO13, PIN_MODE(4) | \
        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
    },
    /* MyRGMII4 -> RGMII4_TD3 -> AE25 */
    {
        PIN_PRG0_PRU1_GPO14, PIN_MODE(4) | \
        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
    },
    /* MyRGMII4 -> RGMII4_TXC -> AG29 */
    {
        PIN_PRG0_PRU1_GPO16, PIN_MODE(4) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyRGMII4 -> RGMII4_TX_CTL -> AF29 */
    {
        PIN_PRG0_PRU1_GPO15, PIN_MODE(4) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    {PINMUX_END}
};

static pinmuxPerCfg_t gRgmii1PinCfg[] =
{
    /* MyRGMII1 -> RGMII1_RD0 -> AC23 */
    {
        PIN_PRG1_PRU0_GPO0, PIN_MODE(4) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyRGMII1 -> RGMII1_RD1 -> AG22 */
    {
        PIN_PRG1_PRU0_GPO1, PIN_MODE(4) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyRGMII1 -> RGMII1_RD2 -> AF22 */
    {
        PIN_PRG1_PRU0_GPO2, PIN_MODE(4) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyRGMII1 -> RGMII1_RD3 -> AJ23 */
    {
        PIN_PRG1_PRU0_GPO3, PIN_MODE(4) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyRGMII1 -> RGMII1_RXC -> AD22 */
    {
        PIN_PRG1_PRU0_GPO6, PIN_MODE(4) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyRGMII1 -> RGMII1_RX_CTL -> AH23 */
    {
        PIN_PRG1_PRU0_GPO4, PIN_MODE(4) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyRGMII1 -> RGMII1_TD0 -> AF24 */
    {
        PIN_PRG1_PRU0_GPO11, PIN_MODE(4) | \
        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
    },
    /* MyRGMII1 -> RGMII1_TD1 -> AJ24 */
    {
        PIN_PRG1_PRU0_GPO12, PIN_MODE(4) | \
        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
    },
    /* MyRGMII1 -> RGMII1_TD2 -> AG24 */
    {
        PIN_PRG1_PRU0_GPO13, PIN_MODE(4) | \
        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
    },
    /* MyRGMII1 -> RGMII1_TD3 -> AD24 */
    {
        PIN_PRG1_PRU0_GPO14, PIN_MODE(4) | \
        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
    },
    /* MyRGMII1 -> RGMII1_TXC -> AE24 */
    {
        PIN_PRG1_PRU0_GPO16, PIN_MODE(4) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyRGMII1 -> RGMII1_TX_CTL -> AC24 */
    {
        PIN_PRG1_PRU0_GPO15, PIN_MODE(4) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    {PINMUX_END}
};

static pinmuxPerCfg_t gRgmii2PinCfg[] =
{
    /* MyRGMII2 -> RGMII2_RD0 -> AE22 */
    {
        PIN_PRG1_PRU1_GPO0, PIN_MODE(4) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyRGMII2 -> RGMII2_RD1 -> AG23 */
    {
        PIN_PRG1_PRU1_GPO1, PIN_MODE(4) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyRGMII2 -> RGMII2_RD2 -> AF23 */
    {
        PIN_PRG1_PRU1_GPO2, PIN_MODE(4) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyRGMII2 -> RGMII2_RD3 -> AD23 */
    {
        PIN_PRG1_PRU1_GPO3, PIN_MODE(4) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyRGMII2 -> RGMII2_RXC -> AE23 */
    {
        PIN_PRG1_PRU1_GPO6, PIN_MODE(4) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyRGMII2 -> RGMII2_RX_CTL -> AH24 */
    {
        PIN_PRG1_PRU1_GPO4, PIN_MODE(4) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyRGMII2 -> RGMII2_TD0 -> AJ25 */
    {
        PIN_PRG1_PRU1_GPO11, PIN_MODE(4) | \
        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
    },
    /* MyRGMII2 -> RGMII2_TD1 -> AH25 */
    {
        PIN_PRG1_PRU1_GPO12, PIN_MODE(4) | \
        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
    },
    /* MyRGMII2 -> RGMII2_TD2 -> AG25 */
    {
        PIN_PRG1_PRU1_GPO13, PIN_MODE(4) | \
        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
    },
    /* MyRGMII2 -> RGMII2_TD3 -> AH26 */
    {
        PIN_PRG1_PRU1_GPO14, PIN_MODE(4) | \
        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
    },
    /* MyRGMII2 -> RGMII2_TXC -> AJ26 */
    {
        PIN_PRG1_PRU1_GPO16, PIN_MODE(4) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyRGMII2 -> RGMII2_TX_CTL -> AJ27 */
    {
        PIN_PRG1_PRU1_GPO15, PIN_MODE(4) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    {PINMUX_END}
};

static pinmuxModuleCfg_t gRgmiiPinCfg[] =
{
    {3, TRUE, gRgmii3PinCfg},
    {4, TRUE, gRgmii4PinCfg},
    {1, TRUE, gRgmii1PinCfg},
    {2, TRUE, gRgmii2PinCfg},
    {PINMUX_END}
};

    c.pdk_jacinto_08_06_00_31/packages/ti/board/src/j721e_evm/J721E_pinmux_data_gesi.c

static pinmuxPerCfg_t gPru_icssg0_rgmii1PinCfg[] =
{
    /* MyPRU_ICSSG0_RGMII1 -> PRG0_RGMII1_RD0 -> AF28 */
    {
        PIN_PRG0_PRU0_GPO0, PIN_MODE(2) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyPRU_ICSSG0_RGMII1 -> PRG0_RGMII1_RD1 -> AE28 */
    {
        PIN_PRG0_PRU0_GPO1, PIN_MODE(2) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyPRU_ICSSG0_RGMII1 -> PRG0_RGMII1_RD2 -> AE27 */
    {
        PIN_PRG0_PRU0_GPO2, PIN_MODE(2) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyPRU_ICSSG0_RGMII1 -> PRG0_RGMII1_RD3 -> AD26 */
    {
        PIN_PRG0_PRU0_GPO3, PIN_MODE(2) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyPRU_ICSSG0_RGMII1 -> PRG0_RGMII1_RXC -> AE26 */
    {
        PIN_PRG0_PRU0_GPO6, PIN_MODE(2) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyPRU_ICSSG0_RGMII1 -> PRG0_RGMII1_RX_CTL -> AD25 */
    {
        PIN_PRG0_PRU0_GPO4, PIN_MODE(2) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyPRU_ICSSG0_RGMII1 -> PRG0_RGMII1_TD0 -> AJ28 */
    {
        PIN_PRG0_PRU0_GPO11, PIN_MODE(2) | \
        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
    },
    /* MyPRU_ICSSG0_RGMII1 -> PRG0_RGMII1_TD1 -> AH27 */
    {
        PIN_PRG0_PRU0_GPO12, PIN_MODE(2) | \
        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
    },
    /* MyPRU_ICSSG0_RGMII1 -> PRG0_RGMII1_TD2 -> AH29 */
    {
        PIN_PRG0_PRU0_GPO13, PIN_MODE(2) | \
        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
    },
    /* MyPRU_ICSSG0_RGMII1 -> PRG0_RGMII1_TD3 -> AG28 */
    {
        PIN_PRG0_PRU0_GPO14, PIN_MODE(2) | \
        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
    },
    /* MyPRU_ICSSG0_RGMII1 -> PRG0_RGMII1_TXC -> AH28 */
    {
        PIN_PRG0_PRU0_GPO16, PIN_MODE(2) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyPRU_ICSSG0_RGMII1 -> PRG0_RGMII1_TX_CTL -> AG27 */
    {
        PIN_PRG0_PRU0_GPO15, PIN_MODE(2) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    {PINMUX_END}
};

static pinmuxPerCfg_t gPru_icssg0_rgmii2PinCfg[] =
{
    /* MyPRU_ICSSG0_RGMII2 -> PRG0_RGMII2_RD0 -> AE29 */
    {
        PIN_PRG0_PRU1_GPO0, PIN_MODE(2) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyPRU_ICSSG0_RGMII2 -> PRG0_RGMII2_RD1 -> AD28 */
    {
        PIN_PRG0_PRU1_GPO1, PIN_MODE(2) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyPRU_ICSSG0_RGMII2 -> PRG0_RGMII2_RD2 -> AD27 */
    {
        PIN_PRG0_PRU1_GPO2, PIN_MODE(2) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyPRU_ICSSG0_RGMII2 -> PRG0_RGMII2_RD3 -> AC25 */
    {
        PIN_PRG0_PRU1_GPO3, PIN_MODE(2) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyPRU_ICSSG0_RGMII2 -> PRG0_RGMII2_RXC -> AC26 */
    {
        PIN_PRG0_PRU1_GPO6, PIN_MODE(2) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyPRU_ICSSG0_RGMII2 -> PRG0_RGMII2_RX_CTL -> AD29 */
    {
        PIN_PRG0_PRU1_GPO4, PIN_MODE(2) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyPRU_ICSSG0_RGMII2 -> PRG0_RGMII2_TD0 -> AG26 */
    {
        PIN_PRG0_PRU1_GPO11, PIN_MODE(2) | \
        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
    },
    /* MyPRU_ICSSG0_RGMII2 -> PRG0_RGMII2_TD1 -> AF27 */
    {
        PIN_PRG0_PRU1_GPO12, PIN_MODE(2) | \
        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
    },
    /* MyPRU_ICSSG0_RGMII2 -> PRG0_RGMII2_TD2 -> AF26 */
    {
        PIN_PRG0_PRU1_GPO13, PIN_MODE(2) | \
        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
    },
    /* MyPRU_ICSSG0_RGMII2 -> PRG0_RGMII2_TD3 -> AE25 */
    {
        PIN_PRG0_PRU1_GPO14, PIN_MODE(2) | \
        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
    },
    /* MyPRU_ICSSG0_RGMII2 -> PRG0_RGMII2_TXC -> AG29 */
    {
        PIN_PRG0_PRU1_GPO16, PIN_MODE(2) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyPRU_ICSSG0_RGMII2 -> PRG0_RGMII2_TX_CTL -> AF29 */
    {
        PIN_PRG0_PRU1_GPO15, PIN_MODE(2) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    {PINMUX_END}
};

static pinmuxModuleCfg_t gPru_icssg0_rgmiiPinCfg[] =
{
    {1, TRUE, gPru_icssg0_rgmii1PinCfg},
    {2, TRUE, gPru_icssg0_rgmii2PinCfg},
    {PINMUX_END}
};

static pinmuxPerCfg_t gPru_icssg1_rgmii1PinCfg[] =
{
    /* MyPRU_ICSSG1_RGMII1 -> PRG1_RGMII1_RD0 -> AC23 */
    {
        PIN_PRG1_PRU0_GPO0, PIN_MODE(2) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyPRU_ICSSG1_RGMII1 -> PRG1_RGMII1_RD1 -> AG22 */
    {
        PIN_PRG1_PRU0_GPO1, PIN_MODE(2) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyPRU_ICSSG1_RGMII1 -> PRG1_RGMII1_RD2 -> AF22 */
    {
        PIN_PRG1_PRU0_GPO2, PIN_MODE(2) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyPRU_ICSSG1_RGMII1 -> PRG1_RGMII1_RD3 -> AJ23 */
    {
        PIN_PRG1_PRU0_GPO3, PIN_MODE(2) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyPRU_ICSSG1_RGMII1 -> PRG1_RGMII1_RXC -> AD22 */
    {
        PIN_PRG1_PRU0_GPO6, PIN_MODE(2) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyPRU_ICSSG1_RGMII1 -> PRG1_RGMII1_RX_CTL -> AH23 */
    {
        PIN_PRG1_PRU0_GPO4, PIN_MODE(2) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyPRU_ICSSG1_RGMII1 -> PRG1_RGMII1_TD0 -> AF24 */
    {
        PIN_PRG1_PRU0_GPO11, PIN_MODE(2) | \
        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
    },
    /* MyPRU_ICSSG1_RGMII1 -> PRG1_RGMII1_TD1 -> AJ24 */
    {
        PIN_PRG1_PRU0_GPO12, PIN_MODE(2) | \
        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
    },
    /* MyPRU_ICSSG1_RGMII1 -> PRG1_RGMII1_TD2 -> AG24 */
    {
        PIN_PRG1_PRU0_GPO13, PIN_MODE(2) | \
        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
    },
    /* MyPRU_ICSSG1_RGMII1 -> PRG1_RGMII1_TD3 -> AD24 */
    {
        PIN_PRG1_PRU0_GPO14, PIN_MODE(2) | \
        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
    },
    /* MyPRU_ICSSG1_RGMII1 -> PRG1_RGMII1_TXC -> AE24 */
    {
        PIN_PRG1_PRU0_GPO16, PIN_MODE(2) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyPRU_ICSSG1_RGMII1 -> PRG1_RGMII1_TX_CTL -> AC24 */
    {
        PIN_PRG1_PRU0_GPO15, PIN_MODE(2) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    {PINMUX_END}
};

static pinmuxPerCfg_t gPru_icssg1_rgmii2PinCfg[] =
{
    /* MyPRU_ICSSG1_RGMII2 -> PRG1_RGMII2_RD0 -> AE22 */
    {
        PIN_PRG1_PRU1_GPO0, PIN_MODE(2) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyPRU_ICSSG1_RGMII2 -> PRG1_RGMII2_RD1 -> AG23 */
    {
        PIN_PRG1_PRU1_GPO1, PIN_MODE(2) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyPRU_ICSSG1_RGMII2 -> PRG1_RGMII2_RD2 -> AF23 */
    {
        PIN_PRG1_PRU1_GPO2, PIN_MODE(2) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyPRU_ICSSG1_RGMII2 -> PRG1_RGMII2_RD3 -> AD23 */
    {
        PIN_PRG1_PRU1_GPO3, PIN_MODE(2) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyPRU_ICSSG1_RGMII2 -> PRG1_RGMII2_RXC -> AE23 */
    {
        PIN_PRG1_PRU1_GPO6, PIN_MODE(2) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyPRU_ICSSG1_RGMII2 -> PRG1_RGMII2_RX_CTL -> AH24 */
    {
        PIN_PRG1_PRU1_GPO4, PIN_MODE(2) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyPRU_ICSSG1_RGMII2 -> PRG1_RGMII2_TD0 -> AJ25 */
    {
        PIN_PRG1_PRU1_GPO11, PIN_MODE(2) | \
        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
    },
    /* MyPRU_ICSSG1_RGMII2 -> PRG1_RGMII2_TD1 -> AH25 */
    {
        PIN_PRG1_PRU1_GPO12, PIN_MODE(2) | \
        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
    },
    /* MyPRU_ICSSG1_RGMII2 -> PRG1_RGMII2_TD2 -> AG25 */
    {
        PIN_PRG1_PRU1_GPO13, PIN_MODE(2) | \
        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
    },
    /* MyPRU_ICSSG1_RGMII2 -> PRG1_RGMII2_TD3 -> AH26 */
    {
        PIN_PRG1_PRU1_GPO14, PIN_MODE(2) | \
        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
    },
    /* MyPRU_ICSSG1_RGMII2 -> PRG1_RGMII2_TXC -> AJ26 */
    {
        PIN_PRG1_PRU1_GPO16, PIN_MODE(2) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyPRU_ICSSG1_RGMII2 -> PRG1_RGMII2_TX_CTL -> AJ27 */
    {
        PIN_PRG1_PRU1_GPO15, PIN_MODE(2) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    {PINMUX_END}
};

static pinmuxModuleCfg_t gPru_icssg1_rgmiiPinCfg[] =
{
    {1, TRUE, gPru_icssg1_rgmii1PinCfg},
    {2, TRUE, gPru_icssg1_rgmii2PinCfg},
    {PINMUX_END}
};

      We did not make changes in the above file.

Doredla Sudheer Kumar said:

If Port-8 is in RMII then it conflict with Mcasp configuration.

  We use CPSW9G by using ethfw in vision_apps.  The port was setted in /vision_apps/utils/ethfw/src/app_ethfw_tirtos.c

static Enet_MacPort gEthAppPorts[] =
{
#if defined(SOC_J721E)
    /* On J721E EVM to use all 8 ports simultaneously, we use below configuration
       RGMII Ports - 1,3,4,8. QSGMII ports - 2,5,6,7 */
    ENET_MAC_PORT_1, /* RGMII */
    //ENET_MAC_PORT_3, /* RGMII */
    ENET_MAC_PORT_4, /* RGMII */
    //ENET_MAC_PORT_8, /* RGMII */
#if defined(ENABLE_QSGMII_PORTS)
    //ENET_MAC_PORT_2, /* QSGMII main */
    //ENET_MAC_PORT_5, /* QSGMII sub */
    ENET_MAC_PORT_6, /* QSGMII sub */
    ENET_MAC_PORT_7, /* QSGMII sub */
#endif
#endif
};

 RGMII port in pdk_jacinto_08_06_00_31/packages/ti/board/src/j721e_evm/J721E_pinmux_data_gesi_cpsw9g.c

static pinmuxModuleCfg_t gRgmiiPinCfg[] =
{
    {3, TRUE, gRgmii3PinCfg},
    {4, TRUE, gRgmii4PinCfg},
    {1, TRUE, gRgmii1PinCfg},
    {2, TRUE, gRgmii2PinCfg},
    {PINMUX_END}
};

static pinmuxModuleCfg_t gSgmiiPinCfg[] =
{
    {3, TRUE, gRgmii3PinCfg},
    {4, TRUE, gRgmii4PinCfg},
    {7, TRUE, gRgmii7PinCfg},
    {8, TRUE, gRgmii8PinCfg},
    {PINMUX_END}
};

static pinmuxModuleCfg_t gQsgmiiPinCfg[] =
{
    {1, TRUE, gRgmii1PinCfg},
    {3, TRUE, gRgmii3PinCfg},
    {4, TRUE, gRgmii4PinCfg},
    {8, TRUE, gRgmii8PinCfg},
    {PINMUX_END}
};

 We think we using RGMII, but there is inconsistent.

Hi,

davied zhang said:

We use CPSW9G by using ethfw in vision_apps.  The port was setted in /vision_apps/utils/ethfw/src/app_ethfw_tirtos.c

From above information, it seems like you are not using Port-3.
I could see you are using Port-1, Port-4 and Port-6, Port-7 under QSGMII Flag.

davied zhang said:

  a. board-support/linux-5.10.162+gitAUTOINC+76b3e88d56-g76b3e88d56/arch/arm64/boot/dts/ti/k3-j721e-gesi-exp-board.dts

This is for Native Linux Driver, when you are using EthFW + Virtual Client on Linux then it will not configure the PinMux.
If you are using Native Linux Driver you should disable the EthFw.

Please make sure at the same either EthFw is loading or Native Linux is enabled for the CPSW9G. (Out of Box Linux SDK Native Linux driver for CPSW9G is not enabled).

davied zhang said:

  b. pdk_jacinto_08_06_00_31/packages/ti/board/src/j721e_evm/J721E_pinmux_data_gesi_cpsw9g

EthFw will use it for the configuration of Ports under "gQsgmiiPinCfg" as per default SDK.

davied zhang said:

c.pdk_jacinto_08_06_00_31/packages/ti/board/src/j721e_evm/J721E_pinmux_data_gesi.c

It is for the PRU configuration, currently which will not be used.


Not sure how Port-3 is Link up messages are observing, as Port-3 is not enabled.

davied zhang said:

 We think we using RGMII, but there is inconsistent.

What do you mean by inconsistent?

Best Regards,
Sudheer

Hi,Sudheer

    Thanks for your support.

Doredla Sudheer Kumar said:

I could see you are using Port-1, Port-4 and Port-6, Port-7 under QSGMII Flag.

    In SDK, it uses Port-1, Port-3,  Port-4, Port-8 under RGMII. Port-1 and Port-4 are using as mac-only port.  We want to use all ports of RGMII as general port, so we add Port-6 Port-7 to used as mac-only port. The settings we want as follows:

static Enet_MacPort gEthAppPorts[] =
{
#if defined(SOC_J721E)
    ENET_MAC_PORT_1, /* RGMII */
    ENET_MAC_PORT_3, /* RGMII */
    ENET_MAC_PORT_4, /* RGMII */
    ENET_MAC_PORT_8, /* RGMII */
    ENET_MAC_PORT_6, /* RGMII-for maconly*/
    ENET_MAC_PORT_7, /* RGMII-for maconly */
#endif
};

  Now we think conflict on Port-3 and Port-8, so we want to disable them and test again. We trying remove PHY0 and PHY15 from RGMII in gesi board:

static Enet_MacPort gEthAppPorts[] =
{
#if defined(SOC_J721E)
    ENET_MAC_PORT_1, /* RGMII */
    //ENET_MAC_PORT_3, /* RGMII */
    ENET_MAC_PORT_4, /* RGMII */
    //ENET_MAC_PORT_8, /* RGMII */
    ENET_MAC_PORT_6, /* RGMII-for maconly*/
    ENET_MAC_PORT_7, /* RGMII-for maconly */
#endif
};

And we remove pinmux from rgmii in pdk_jacinto_08_06_00_31/packages/ti/board/src/j721e_evm/J721E_pinmux_data_gesi_cpsw9g.c

static pinmuxModuleCfg_t gRgmiiPinCfg[] =
{
    //{3, TRUE, gRgmii3PinCfg},
    {4, TRUE, gRgmii4PinCfg},
    {1, TRUE, gRgmii1PinCfg},
    //{2, TRUE, gRgmii2PinCfg},
    {PINMUX_END}
};

static pinmuxModuleCfg_t gQsgmiiPinCfg[] =
{
    {1, TRUE, gRgmii1PinCfg},
    //{3, TRUE, gRgmii3PinCfg},
    {4, TRUE, gRgmii4PinCfg},
    //{8, TRUE, gRgmii8PinCfg},
    {PINMUX_END}
};

Doredla Sudheer Kumar said:

What do you mean by inconsistent?

We have diabled Port-3/Port-8, and remove pinmux of them. But in log we can get phy0 and phy15.

source ./vision_apps_init.sh 
root@j7-evm:/opt/vision_apps# [MCU2_0]      3.601752 s: CIO: Init ... Done !!!
[MCU2_0]      3.601827 s: ### CPU Frequency = 1000000000 Hz
[MCU2_0]      3.601866 s: CPU is running FreeRTOS
[MCU2_0]      3.601890 s: APP: Init ... !!!
[MCU2_0]      3.601912 s: SCICLIENT: Init ... !!!
[MCU2_0]      3.602160 s: SCICLIENT: DMSC FW version [8.6.3--v08.06.03 (Chill Capybar]
[MCU2_0]      3.602208 s: SCICLIENT: DMSC FW revision 0x8  
[MCU2_0]      3.602240 s: SCICLIENT: DMSC FW ABI revision 3.1
[MCU2_0]      3.602275 s: SCICLIENT: Init ... Done !!!
[MCU2_0]      3.602300 s: UDMA: Init ... !!!
[MCU2_0]      3.603589 s: UDMA: Init ... Done !!!
[MCU2_0]      3.603652 s: MEM: Init ... !!!
[MCU2_0]      3.603696 s: MEM: Created heap (DDR_LOCAL_MEM, id=0, flags=0x00000004) @ d9000000 of size 16777216 bytes !!!
[MCU2_0]      3.603768 s: MEM: Created heap (L3_MEM, id=1, flags=0x00000000) @ 3600000 of size 262144 bytes !!!
[MCU2_0]      3.603829 s: MEM: Init ... Done !!!
[MCU2_0]      3.603853 s: IPC: Init ... !!!
[MCU2_0]      3.603915 s: IPC: 6 CPUs participating in IPC !!!
[MCU2_0]      3.603965 s: IPC: Waiting for HLOS to be ready ... !!!
[MCU2_0]     13.348243 s: IPC: HLOS is ready !!!
[MCU2_0]     13.363533 s: IPC: Init ... Done !!!
[MCU2_0]     13.363599 s: APP: Syncing with 5 CPUs ... !!!
[MCU2_0]     13.543695 s: APP: Syncing with 5 CPUs ... Done !!!
[MCU2_0]     13.543918 s: REMOTE_SERVICE: Init ... !!!
[MCU2_0]     13.545436 s: REMOTE_SERVICE: Init ... Done !!!
[MCU2_0]     13.545512 s: ETHFW: Init ... !!!
[MCU2_0]     13.653008 s: Warning: Using 6 MAC address(es) from static pool
[MCU2_0]     13.653119 s: ETHFW: Shared multicasts (software fanout):
[MCU2_0]     13.653165 s: ETHFW: Reserved multicasts:
[MCU2_0]     13.653195 s:   01:80:c2:00:00:0e
[MCU2_0]     13.653243 s:   01:1b:19:00:00:00
[MCU2_0]     13.653509 s: EnetMcm: CPSW_9G on MAIN NAVSS
[MCU2_0]     13.662695 s: Mdio_open: MDIO manual mode enabled
[MCU2_0]     13.665273 s: EnetMcm_enablePorts: PHY 0 is alive
[MCU2_0]     13.665580 s: EnetMcm_enablePorts: PHY 3 is alive
[MCU2_0]     13.666223 s: EnetMcm_enablePorts: PHY 12 is alive
[MCU2_0]     13.666477 s: EnetMcm_enablePorts: PHY 15 is alive
[MCU2_0]     13.667968 s: EnetPhy_bindDriver: PHY 12: OUI:080028 Model:23 Ver:01 <-> 'dp83867' : OK
[MCU2_0]     13.668469 s: EnetPhy_bindDriver: PHY 3: OUI:080028 Model:23 Ver:01 <-> 'dp83867' : OK
[MCU2_0]     13.670563 s: 
[MCU2_0] ETHFW Version   : 0.02.00
[MCU2_0]     13.670644 s: ETHFW Build Date: Jan 30, 2024
[MCU2_0]     13.670678 s: ETHFW Build Time: 17:37:42
[MCU2_0]     13.670704 s: ETHFW Commit SHA: d2655bba
[MCU2_0]     13.670772 s: ETHFW: Init ... DONE !!!
[MCU2_0]     13.670804 s: ETHFW: Remove server Init ... !!!
[MCU2_0]     13.670975 s: CpswProxyServer: Virtual port configuration:
[MCU2_0]     13.671029 s:   mpu_1_0 <-> Switch port 0: mpu_1_0_ethswitch-device-0
[MCU2_0]     13.671075 s:   mcu_2_1 <-> Switch port 1: mcu_2_1_ethswitch-device-1
[MCU2_0]     13.671117 s:   mpu_1_0 <-> MAC port 6: mpu_1_0_ethmac-device-6
[MCU2_0]     13.671157 s:   mcu_2_1 <-> MAC port 7: mcu_2_1_ethmac-device-7
[MCU2_0]     13.672186 s: CpswProxyServer: initialization completed (core: mcu2_0)
[MCU2_0]     13.672253 s: ETHFW: Remove server Init ... DONE !!!
[MCU2_0]     13.673372 s: Starting lwIP, local interface IP is dhcp-enabled
[MCU2_0]     13.681299 s: Host MAC address: 70:ff:76:1d:92:c3
[MCU2_0]     13.685358 s: [LWIPIF_LWIP] Enet LLD netif initialized successfully
[MCU2_0]     13.685452 s: Added interface 'ti1', IP is 0.0.0.0
[MCU2_0]     13.721486 s: FVID2: Init ... !!!
[MCU2_0]     13.721592 s: FVID2: Init ... Done !!!
[MCU2_0]     13.721645 s: DSS: Init ... !!!
[MCU2_0]     13.721676 s: DSS: Display type is eDP !!!
[MCU2_0]     13.721702 s: DSS: M2M Path is enabled !!!
[MCU2_0]     13.721729 s: DSS: SoC init ... !!!
[MCU2_0]     13.721753 s: SCICLIENT: Sciclient_pmSetModuleState module=152 state=2
[MCU2_0]     13.721976 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]     13.722019 s: SCICLIENT: Sciclient_pmSetModuleState module=297 state=2
[MCU2_0]     13.722208 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]     13.722244 s: SCICLIENT: Sciclient_pmSetModuleState module=151 state=2
[MCU2_0]     13.722390 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]     13.722424 s: SCICLIENT: Sciclient_pmSetModuleClkParent module=152 clk=9 parent=11
[MCU2_0]     13.722653 s: SCICLIENT: Sciclient_pmSetModuleClkParent success
[MCU2_0]     13.722706 s: SCICLIENT: Sciclient_pmSetModuleClkParent module=152 clk=13 parent=18
[MCU2_0]     13.722825 s: SCICLIENT: Sciclient_pmSetModuleClkParent success
[MCU2_0]     13.722860 s: SCICLIENT: Sciclient_pmSetModuleClkParent module=152 clk=1 parent=2
[MCU2_0]     13.722958 s: SCICLIENT: Sciclient_pmSetModuleClkParent success
[MCU2_0]     13.722992 s: SCICLIENT: Sciclient_pmSetModuleClkFreq module=152 clk=1 freq=148500000
[MCU2_0]     13.724237 s: SCICLIENT: Sciclient_pmSetModuleClkFreq success
[MCU2_0]     13.724286 s: SCICLIENT: Sciclient_pmModuleClkRequest module=152 clk=1 state=2 flag=0
[MCU2_0]     13.724450 s: SCICLIENT: Sciclient_pmModuleClkRequest success
[MCU2_0]     13.724567 s: DSS: SoC init ... Done !!!
[MCU2_0]     13.724596 s: DSS: Board init ... !!!
[MCU2_0]     13.724620 s: DSS: Board init ... Done !!!
[MCU2_0]     13.743710 s: DSS: Init ... Done !!!
[MCU2_0]     13.743783 s: VHWA: VPAC Init ... !!!
[MCU2_0]     13.743814 s: SCICLIENT: Sciclient_pmSetModuleState module=290 state=2
[MCU2_0]     13.744041 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]     13.744087 s: VHWA: LDC Init ... !!!
[MCU2_0]     13.747829 s: VHWA: LDC Init ... Done !!!
[MCU2_0]     13.747900 s: VHWA: MSC Init ... !!!
[MCU2_0]     13.760267 s: VHWA: MSC Init ... Done !!!
[MCU2_0]     13.760364 s: VHWA: NF Init ... !!!
[MCU2_0]     13.762427 s: VHWA: NF Init ... Done !!!
[MCU2_0]     13.762607 s: VHWA: VISS Init ... !!!
[MCU2_0]     13.773905 s: VHWA: VISS Init ... Done !!!
[MCU2_0]     13.773974 s: VHWA: VPAC Init ... Done !!!
[MCU2_0]     13.774022 s:  VX_ZONE_INIT:Enabled
[MCU2_0]     13.774054 s:  VX_ZONE_ERROR:Enabled
[MCU2_0]     13.774080 s:  VX_ZONE_WARNING:Enabled
[MCU2_0]     13.775728 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target MCU2-0 
[MCU2_0]     13.776006 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target VPAC_NF 
[MCU2_0]     13.776243 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target VPAC_LDC1 
[MCU2_0]     13.776633 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target VPAC_MSC1 
[MCU2_0]     13.776931 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target VPAC_MSC2 
[MCU2_0]     13.777254 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target VPAC_VISS1 
[MCU2_0]     13.777654 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target CAPTURE1 
[MCU2_0]     13.777948 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target CAPTURE2 
[MCU2_0]     13.778221 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target DISPLAY1 
[MCU2_0]     13.778600 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target DISPLAY2 
[MCU2_0]     13.778869 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target CSITX 
[MCU2_0]     13.779164 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target CAPTURE3 
[MCU2_0]     13.779433 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target CAPTURE4 
[MCU2_0]     13.779847 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target CAPTURE5 
[MCU2_0]     13.780132 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target CAPTURE6 
[MCU2_0]     13.780394 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target CAPTURE7 
[MCU2_0]     13.780795 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target CAPTURE8 
[MCU2_0]     13.781060 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target DSS_M2M1 
[MCU2_0]     13.781294 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target DSS_M2M2 
[MCU2_0]     13.781693 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target DSS_M2M3 
[MCU2_0]     13.781973 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target DSS_M2M4 
[MCU2_0]     13.782033 s:  VX_ZONE_INIT:[tivxInitLocal:130] Initialization Done !!!
[MCU2_0]     13.782072 s: APP: OpenVX Target kernel init ... !!!
[MCU2_0]     13.803169 s: APP: OpenVX Target kernel init ... Done !!!
[MCU2_0]     13.803238 s: CSI2RX: Init ... !!!
[MCU2_0]     13.803268 s: SCICLIENT: Sciclient_pmSetModuleState module=25 state=2
[MCU2_0]     13.803400 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]     13.803443 s: SCICLIENT: Sciclient_pmSetModuleState module=26 state=2
[MCU2_0]     13.803726 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]     13.803772 s: SCICLIENT: Sciclient_pmSetModuleState module=27 state=2
[MCU2_0]     13.803919 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]     13.803954 s: SCICLIENT: Sciclient_pmSetModuleState module=147 state=2
[MCU2_0]     13.804058 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]     13.804091 s: SCICLIENT: Sciclient_pmSetModuleState module=148 state=2
[MCU2_0]     13.804177 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]     13.804406 s: CSI2RX: Init ... Done !!!
[MCU2_0]     13.804447 s: CSI2TX: Init ... !!!
[MCU2_0]     13.804591 s: SCICLIENT: Sciclient_pmSetModuleState module=25 state=2
[MCU2_0]     13.804702 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]     13.804744 s: SCICLIENT: Sciclient_pmSetModuleState module=28 state=2
[MCU2_0]     13.804888 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]     13.804923 s: SCICLIENT: Sciclient_pmSetModuleState module=296 state=2
[MCU2_0]     13.805047 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]     13.805143 s: CSI2TX: Init ... Done !!!
[MCU2_0]     13.805178 s: ISS: Init ... !!!
[MCU2_0]     13.805215 s: IssSensor_Init ... Done !!!
[MCU2_0]     13.805291 s: IttRemoteServer_Init ... Done !!!
[MCU2_0]     13.805326 s: VISS REMOTE SERVICE: Init ... !!!
[MCU2_0]     13.805388 s: VISS REMOTE SERVICE: Init ... Done !!!
[MCU2_0]     13.805420 s: UDMA Copy: Init ... !!!
[MCU2_0]     13.807561 s: UDMA Copy: Init ... Done !!!
[MCU2_0]     13.807676 s: APP: Init ... Done !!!
[MCU2_0]     13.807712 s: APP: Run ... !!!
[MCU2_0]     13.807736 s: IPC: Starting echo test ...
[MCU2_0]     13.808660 s: Function:CpswProxyServer_attachExtHandlerCb,HostId:0,CpswType:6
[MCU2_0]     13.810979 s: APP: Run ... Done !!!
[MCU2_0]     13.812784 s: IPC: Echo status: mpu1_0[x] mcu2_0[s] mcu2_1[.] C66X_1[P] C66X_2[.] C7X_1[.] 
[MCU2_0]     13.812904 s: IPC: Echo status: mpu1_0[x] mcu2_0[s] mcu2_1[P] C66X_1[P] C66X_2[.] C7X_1[.] 
[MCU2_0]     13.813103 s: IPC: Echo status: mpu1_0[x] mcu2_0[s] mcu2_1[P] C66X_1[P] C66X_2[P] C7X_1[.] 
[MCU2_0]     13.813212 s: IPC: Echo status: mpu1_0[x] mcu2_0[s] mcu2_1[P] C66X_1[P] C66X_2[P] C7X_1[P] 
[MCU2_0]     14.813573 s: Assertion @ Line: 1354 in enet_mcm.c: false : failed !!!
[MCU2_0]     16.553357 s: Function:CpswProxyServer_registerMacHandlerCb,HostId:0,Handle:a3a4f5bc,CoreKey:38acb7e6, MacAddress:70:ff:76:1d:92:c1, FlowIdx:172, FlowIdxOffset:0
[MCU2_0]     16.556574 s: Cpsw_ioctlInternal: CPSW: Registered MAC address. ALE entry:10, Policer Entry:1
[MCU2_0]     16.584926 s: Function:CpswProxyServer_filterAddMacHandlerCb,HostId:0,Handle:a3a4f5bc,CoreKey:38acb7e6, MacAddress:33:33:0:0:0:1, vlanId:0, FlowIdx:172, FlowIdOffset:0
[MCU2_0]     16.588417 s: Function:CpswProxyServer_filterAddMacHandlerCb,HostId:0,Handle:a3a4f5bc,CoreKey:38acb7e6, MacAddress:1:0:5e:0:0:1, vlanId:0, FlowIdx:172, FlowIdOffset:0
[MCU2_0]     16.591936 s: Function:CpswProxyServer_filterAddMacHandlerCb,HostId:0,Handle:a3a4f5bc,CoreKey:38acb7e6, MacAddress:33:33:ff:1d:92:c1, vlanId:0, FlowIdx:172, FlowIdOffset:0
[MCU2_0]     16.792640 s: Function:CpswProxyServer_filterAddMacHandlerCb,HostId:0,Handle:a3a4f5bc,CoreKey:38acb7e6, MacAddress:1:80:c2:0:0:0, vlanId:0, FlowIdx:172, FlowIdOffset:0
[MCU2_0]     16.796172 s: Function:CpswProxyServer_filterAddMacHandlerCb,HostId:0,Handle:a3a4f5bc,CoreKey:38acb7e6, MacAddress:1:80:c2:0:0:3, vlanId:0, FlowIdx:172, FlowIdOffset:0
[MCU2_0]     16.799722 s: Function:CpswProxyServer_filterAddMacHandlerCb,HostId:0,Handle:a3a4f5bc,CoreKey:38acb7e6, MacAddress:1:80:c2:0:0:e, vlanId:0, FlowIdx:172, FlowIdOffset:0
[MCU2_0]     16.799874 s: CpswProxyServer_isRsvdMcast: Reserved mcast cannot be added to filter
[MCU2_0]     16.951723 s: Function:CpswProxyServer_filterAddMacHandlerCb,HostId:0,Handle:a3a4f5bc,CoreKey:38acb7e6, MacAddress:33:33:0:0:0:fb, vlanId:0, FlowIdx:172, FlowIdOffset:0
[MCU2_0]     18.168660 s: Cpsw_handleLinkUp: Port 1: Link up: 1-Gbps Full-Duplex
[MCU2_0]     18.473984 s: Function:CpswProxyServer_filterAddMacHandlerCb,HostId:0,Handle:a3a4f5bc,CoreKey:38acb7e6, MacAddress:33:33:0:1:0:3, vlanId:0, FlowIdx:172, FlowIdOffset:0
[MCU2_1]      3.549010 s: CIO: Init ... Done !!!
[MCU2_1]      3.549083 s: ### CPU Frequency = 1000000000 Hz
[MCU2_1]      3.549123 s: CPU is running FreeRTOS
[MCU2_1]      3.549148 s: APP: Init ... !!!
[MCU2_1]      3.549170 s: SCICLIENT: Init ... !!!
[MCU2_1]      3.549422 s: SCICLIENT: DMSC FW version [8.6.3--v08.06.03 (Chill Capybar]
[MCU2_1]      3.549473 s: SCICLIENT: DMSC FW revision 0x8  
[MCU2_1]      3.549504 s: SCICLIENT: DMSC FW ABI revision 3.1
[MCU2_1]      3.549554 s: SCICLIENT: Init ... Done !!!
[MCU2_1]      3.549585 s: UDMA: Init ... !!!
[MCU2_1]      3.551040 s: UDMA: Init ... Done !!!
[MCU2_1]      3.551101 s: MEM: Init ... !!!
[MCU2_1]      3.551145 s: MEM: Created heap (DDR_LOCAL_MEM, id=0, flags=0x00000004) @ da000000 of size 16777216 bytes !!!
[MCU2_1]      3.551220 s: MEM: Created heap (L3_MEM, id=1, flags=0x00000001) @ 3640000 of size 262144 bytes !!!
[MCU2_1]      3.551281 s: MEM: Init ... Done !!!
[MCU2_1]      3.551305 s: IPC: Init ... !!!
[MCU2_1]      3.551366 s: IPC: 6 CPUs participating in IPC !!!
[MCU2_1]      3.551416 s: IPC: Waiting for HLOS to be ready ... !!!
[MCU2_1]     13.528349 s: IPC: HLOS is ready !!!
[MCU2_1]     13.543581 s: IPC: Init ... Done !!!
[MCU2_1]     13.543647 s: APP: Syncing with 5 CPUs ... !!!
[MCU2_1]     13.543694 s: APP: Syncing with 5 CPUs ... Done !!!
[MCU2_1]     13.543731 s: REMOTE_SERVICE: Init ... !!!
[MCU2_1]     13.545441 s: REMOTE_SERVICE: Init ... Done !!!
[MCU2_1]     13.545508 s: FVID2: Init ... !!!
[MCU2_1]     13.545589 s: FVID2: Init ... Done !!!
[MCU2_1]     13.545625 s: VHWA: DMPAC: Init ... !!!
[MCU2_1]     13.545651 s: SCICLIENT: Sciclient_pmSetModuleState module=48 state=2
[MCU2_1]     13.546073 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_1]     13.546114 s: SCICLIENT: Sciclient_pmSetModuleState module=305 state=2
[MCU2_1]     13.546568 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_1]     13.546606 s: VHWA: DOF Init ... !!!
[MCU2_1]     13.554829 s: VHWA: DOF Init ... Done !!!
[MCU2_1]     13.554893 s: VHWA: SDE Init ... !!!
[MCU2_1]     13.557623 s: VHWA: SDE Init ... Done !!!
[MCU2_1]     13.557685 s: VHWA: DMPAC: Init ... Done !!!
[MCU2_1]     13.557733 s:  VX_ZONE_INIT:Enabled
[MCU2_1]     13.557762 s:  VX_ZONE_ERROR:Enabled
[MCU2_1]     13.557788 s:  VX_ZONE_WARNING:Enabled
[MCU2_1]     13.559219 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target MCU2-1 
[MCU2_1]     13.559461 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target DMPAC_SDE 
[MCU2_1]     13.559708 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target DMPAC_DOF 
[MCU2_1]     13.559764 s:  VX_ZONE_INIT:[tivxInitLocal:130] Initialization Done !!!
[MCU2_1]     13.559803 s: APP: OpenVX Target kernel init ... !!!
[MCU2_1]     13.560070 s: APP: OpenVX Target kernel init ... Done !!!
[MCU2_1]     13.560112 s: UDMA Copy: Init ... !!!
[MCU2_1]     13.561938 s: UDMA Copy: Init ... Done !!!
[MCU2_1]     13.562009 s: APP: Init ... Done !!!
[MCU2_1]     13.562039 s: APP: Run ... !!!
[MCU2_1]     13.562065 s: IPC: Starting echo test ...
[MCU2_1]     13.564635 s: APP: Run ... Done !!!
[MCU2_1]     13.565822 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[s] C66X_1[P] C66X_2[.] C7X_1[.] 
[MCU2_1]     13.565942 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[s] C66X_1[P] C66X_2[P] C7X_1[.] 
[MCU2_1]     13.566032 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[s] C66X_1[P] C66X_2[P] C7X_1[P] 
[MCU2_1]     13.813034 s: IPC: Echo status: mpu1_0[x] mcu2_0[P] mcu2_1[s] C66X_1[P] C66X_2[P] C7X_1[P] 
[C6x_1 ]      3.612892 s: CIO: Init ... Done !!!
[C6x_1 ]      3.612917 s: ### CPU Frequency = 1350000000 Hz
[C6x_1 ]      3.612927 s: CPU is running FreeRTOS
[C6x_1 ]      3.612935 s: APP: Init ... !!!
[C6x_1 ]      3.612943 s: SCICLIENT: Init ... !!!
[C6x_1 ]      3.613157 s: SCICLIENT: DMSC FW version [8.6.3--v08.06.03 (Chill Capybar]
[C6x_1 ]      3.613168 s: SCICLIENT: DMSC FW revision 0x8  
[C6x_1 ]      3.613177 s: SCICLIENT: DMSC FW ABI revision 3.1
[C6x_1 ]      3.613187 s: SCICLIENT: Init ... Done !!!
[C6x_1 ]      3.613196 s: UDMA: Init ... !!!
[C6x_1 ]      3.614653 s: UDMA: Init ... Done !!!
[C6x_1 ]      3.614673 s: MEM: Init ... !!!
[C6x_1 ]      3.614686 s: MEM: Created heap (DDR_LOCAL_MEM, id=0, flags=0x00000004) @ dc000000 of size 16777216 bytes !!!
[C6x_1 ]      3.614703 s: MEM: Created heap (L2_MEM, id=2, flags=0x00000001) @ 800000 of size 229376 bytes !!!
[C6x_1 ]      3.614718 s: MEM: Created heap (DDR_SCRATCH_MEM, id=4, flags=0x00000001) @ dd000000 of size 50331648 bytes !!!
[C6x_1 ]      3.614734 s: MEM: Init ... Done !!!
[C6x_1 ]      3.614743 s: IPC: Init ... !!!
[C6x_1 ]      3.614762 s: IPC: 6 CPUs participating in IPC !!!
[C6x_1 ]      3.614775 s: IPC: Waiting for HLOS to be ready ... !!!
[C6x_1 ]     12.870273 s: IPC: HLOS is ready !!!
[C6x_1 ]     12.874084 s: IPC: Init ... Done !!!
[C6x_1 ]     12.874114 s: APP: Syncing with 5 CPUs ... !!!
[C6x_1 ]     13.543694 s: APP: Syncing with 5 CPUs ... Done !!!
[C6x_1 ]     13.543707 s: REMOTE_SERVICE: Init ... !!!
[C6x_1 ]     13.544338 s: REMOTE_SERVICE: Init ... Done !!!
[C6x_1 ]     13.544372 s:  VX_ZONE_INIT:Enabled
[C6x_1 ]     13.544382 s:  VX_ZONE_ERROR:Enabled
[C6x_1 ]     13.544391 s:  VX_ZONE_WARNING:Enabled
[C6x_1 ]     13.545162 s:  VX_ZONE_INIT:[tivxInitLocal:130] Initialization Done !!!
[C6x_1 ]     13.545176 s: APP: OpenVX Target kernel init ... !!!
[C6x_1 ]     13.545435 s: APP: OpenVX Target kernel init ... Done !!!
[C6x_1 ]     13.545450 s: UDMA Copy: Init ... !!!
[C6x_1 ]     13.549039 s: UDMA Copy: Init ... Done !!!
[C6x_1 ]     13.549060 s: APP: Init ... Done !!!
[C6x_1 ]     13.549068 s: APP: Run ... !!!
[C6x_1 ]     13.549076 s: IPC: Starting echo test ...
[C6x_1 ]     13.550107 s: APP: Run ... Done !!!
[C6x_1 ]     13.550416 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] C66X_1[s] C66X_2[x] C7X_1[P] 
[C6x_1 ]     13.550891 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] C66X_1[s] C66X_2[P] C7X_1[P] 
[C6x_1 ]     13.565190 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[P] C66X_1[s] C66X_2[P] C7X_1[P] 
[C6x_1 ]     13.812423 s: IPC: Echo status: mpu1_0[x] mcu2_0[P] mcu2_1[P] C66X_1[s] C66X_2[P] C7X_1[P] 
[C6x_2 ]      3.699933 s: CIO: Init ... Done !!!
[C6x_2 ]      3.699959 s: ### CPU Frequency = 1350000000 Hz
[C6x_2 ]      3.699969 s: CPU is running FreeRTOS
[C6x_2 ]      3.699977 s: APP: Init ... !!!
[C6x_2 ]      3.699985 s: SCICLIENT: Init ... !!!
[C6x_2 ]      3.700189 s: SCICLIENT: DMSC FW version [8.6.3--v08.06.03 (Chill Capybar]
[C6x_2 ]      3.700201 s: SCICLIENT: DMSC FW revision 0x8  
[C6x_2 ]      3.700210 s: SCICLIENT: DMSC FW ABI revision 3.1
[C6x_2 ]      3.700220 s: SCICLIENT: Init ... Done !!!
[C6x_2 ]      3.700230 s: UDMA: Init ... !!!
[C6x_2 ]      3.701688 s: UDMA: Init ... Done !!!
[C6x_2 ]      3.701709 s: MEM: Init ... !!!
[C6x_2 ]      3.701722 s: MEM: Created heap (DDR_LOCAL_MEM, id=0, flags=0x00000004) @ e0000000 of size 16777216 bytes !!!
[C6x_2 ]      3.701740 s: MEM: Created heap (L2_MEM, id=2, flags=0x00000001) @ 800000 of size 229376 bytes !!!
[C6x_2 ]      3.701756 s: MEM: Created heap (DDR_SCRATCH_MEM, id=4, flags=0x00000001) @ e1000000 of size 50331648 bytes !!!
[C6x_2 ]      3.701772 s: MEM: Init ... Done !!!
[C6x_2 ]      3.701780 s: IPC: Init ... !!!
[C6x_2 ]      3.701800 s: IPC: 6 CPUs participating in IPC !!!
[C6x_2 ]      3.701813 s: IPC: Waiting for HLOS to be ready ... !!!
[C6x_2 ]     12.970374 s: IPC: HLOS is ready !!!
[C6x_2 ]     12.973954 s: IPC: Init ... Done !!!
[C6x_2 ]     12.973983 s: APP: Syncing with 5 CPUs ... !!!
[C6x_2 ]     13.543695 s: APP: Syncing with 5 CPUs ... Done !!!
[C6x_2 ]     13.543709 s: REMOTE_SERVICE: Init ... !!!
[C6x_2 ]     13.544348 s: REMOTE_SERVICE: Init ... Done !!!
[C6x_2 ]     13.544381 s:  VX_ZONE_INIT:Enabled
[C6x_2 ]     13.544391 s:  VX_ZONE_ERROR:Enabled
[C6x_2 ]     13.544401 s:  VX_ZONE_WARNING:Enabled
[C6x_2 ]     13.545175 s:  VX_ZONE_INIT:[tivxInitLocal:130] Initialization Done !!!
[C6x_2 ]     13.545188 s: APP: OpenVX Target kernel init ... !!!
[C6x_2 ]     13.545447 s: APP: OpenVX Target kernel init ... Done !!!
[C6x_2 ]     13.545462 s: UDMA Copy: Init ... !!!
[C6x_2 ]     13.549367 s: UDMA Copy: Init ... Done !!!
[C6x_2 ]     13.549390 s: APP: Init ... Done !!!
[C6x_2 ]     13.549399 s: APP: Run ... !!!
[C6x_2 ]     13.549407 s: IPC: Starting echo test ...
[C6x_2 ]     13.550537 s: APP: Run ... Done !!!
[C6x_2 ]     13.550889 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] C66X_1[P] C66X_2[s] C7X_1[.] 
[C6x_2 ]     13.550924 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] C66X_1[P] C66X_2[s] C7X_1[P] 
[C6x_2 ]     13.565217 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[P] C66X_1[P] C66X_2[s] C7X_1[P] 
[C6x_2 ]     13.812456 s: IPC: Echo status: mpu1_0[x] mcu2_0[P] mcu2_1[P] C66X_1[P] C66X_2[s] C7X_1[P] 
[C7x_1 ]      3.930815 s: CIO: Init ... Done !!!
[C7x_1 ]      3.930829 s: ### CPU Frequency = 1000000000 Hz
[C7x_1 ]      3.930841 s: CPU is running FreeRTOS
[C7x_1 ]      3.930849 s: APP: Init ... !!!
[C7x_1 ]      3.930857 s: SCICLIENT: Init ... !!!
[C7x_1 ]      3.931061 s: SCICLIENT: DMSC FW version [8.6.3--v08.06.03 (Chill Capybar]
[C7x_1 ]      3.931075 s: SCICLIENT: DMSC FW revision 0x8  
[C7x_1 ]      3.931085 s: SCICLIENT: DMSC FW ABI revision 3.1
[C7x_1 ]      3.931097 s: SCICLIENT: Init ... Done !!!
[C7x_1 ]      3.931106 s: UDMA: Init ... !!!
[C7x_1 ]      3.932234 s: UDMA: Init ... Done !!!
[C7x_1 ]      3.932246 s: MEM: Init ... !!!
[C7x_1 ]      3.932257 s: MEM: Created heap (DDR_LOCAL_MEM, id=0, flags=0x00000004) @ 117000000 of size 268435456 bytes !!!
[C7x_1 ]      3.932277 s: MEM: Created heap (L3_MEM, id=1, flags=0x00000001) @ 70020000 of size 8159232 bytes !!!
[C7x_1 ]      3.932295 s: MEM: Created heap (L2_MEM, id=2, flags=0x00000001) @ 64800000 of size 458752 bytes !!!
[C7x_1 ]      3.932312 s: MEM: Created heap (L1_MEM, id=3, flags=0x00000001) @ 64e00000 of size 16384 bytes !!!
[C7x_1 ]      3.932329 s: MEM: Created heap (DDR_SCRATCH_MEM, id=4, flags=0x00000001) @ 100000000 of size 385875968 bytes !!!
[C7x_1 ]      3.932347 s: MEM: Init ... Done !!!
[C7x_1 ]      3.932355 s: IPC: Init ... !!!
[C7x_1 ]      3.932369 s: IPC: 6 CPUs participating in IPC !!!
[C7x_1 ]      3.932382 s: IPC: Waiting for HLOS to be ready ... !!!
[C7x_1 ]     13.073759 s: IPC: HLOS is ready !!!
[C7x_1 ]     13.075718 s: IPC: Init ... Done !!!
[C7x_1 ]     13.075732 s: APP: Syncing with 5 CPUs ... !!!
[C7x_1 ]     13.543695 s: APP: Syncing with 5 CPUs ... Done !!!
[C7x_1 ]     13.543713 s: REMOTE_SERVICE: Init ... !!!
[C7x_1 ]     13.543862 s: REMOTE_SERVICE: Init ... Done !!!
[C7x_1 ]     13.543884 s:  VX_ZONE_INIT:Enabled
[C7x_1 ]     13.543895 s:  VX_ZONE_ERROR:Enabled
[C7x_1 ]     13.543905 s:  VX_ZONE_WARNING:Enabled
[C7x_1 ]     13.544053 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-1 
[C7x_1 ]     13.544117 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-1_PRI_2 
[C7x_1 ]     13.544178 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-1_PRI_3 
[C7x_1 ]     13.544288 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-1_PRI_4 
[C7x_1 ]     13.544352 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-1_PRI_5 
[C7x_1 ]     13.544419 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-1_PRI_6 
[C7x_1 ]     13.544538 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-1_PRI_7 
[C7x_1 ]     13.544602 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-1_PRI_8 
[C7x_1 ]     13.544623 s:  VX_ZONE_INIT:[tivxInitLocal:130] Initialization Done !!!
[C7x_1 ]     13.544635 s: APP: OpenVX Target kernel init ... !!!
[C7x_1 ]     13.544781 s: APP: OpenVX Target kernel init ... Done !!!
[C7x_1 ]     13.544795 s: APP: Init ... Done !!!
[C7x_1 ]     13.544805 s: APP: Run ... !!!
[C7x_1 ]     13.544813 s: IPC: Starting echo test ...
[C7x_1 ]     13.544962 s: APP: Run ... Done !!!
[C7x_1 ]     13.550418 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] C66X_1[P] C66X_2[x] C7X_1[s] 
[C7x_1 ]     13.550884 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] C66X_1[P] C66X_2[P] C7X_1[s] 
[C7x_1 ]     13.565244 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[P] C66X_1[P] C66X_2[P] C7X_1[s] 
[C7x_1 ]     13.813060 s: IPC: Echo status: mpu1_0[x] mcu2_0[P] mcu2_1[P] C66X_1[P] C66X_2[P] C7X_1[s] 

So why phy0 and phy15 is alive?

Best Regards,

Zhang

Hi,

davied zhang said:

Doredla Sudheer Kumar said:

I could see you are using Port-1, Port-4 and Port-6, Port-7 under QSGMII Flag.

    In SDK, it uses Port-1, Port-3,  Port-4, Port-8 under RGMII. Port-1 and Port-4 are using as mac-only port.  We want to use all ports of RGMII as general port, so we add Port-6 Port-7 to used as mac-only port. The settings we want as follows:

Understood made changes for testing by disabling Port-3 & Port-8.

davied zhang said:

So why phy0 and phy15 is alive?

MDIO will check for all available PHYs from address 0 to 31 and show all PHYs detected.
But driver will be loaded for the PHYs being used, mapped with MAC Ports. If you see above binding PHY driver not happen for PHY0 & PHY15.

Are you observing any issue after disable of Port-3 & Port-8.

Best Regards,
Sudheer

Hi,Sudheer

     Thanks for your support.

Doredla Sudheer Kumar said:

Are you observing any issue after disable of Port-3 & Port-8.

    We have tested it for a weeks. Now we found previous problems: no supported caps found, the log as follow:

[MCU2_0]   1478.787122 s: EnetPhy_enableState: PHY 12: no supported caps found
[MCU2_0]   1478.787415 s: EnetPhy_enableState: PHY 3: no supported caps found
[MCU2_0]   1478.787687 s: EnetPhy_enableState: PHY 18: no supported caps found
[MCU2_0]   1478.788064 s: EnetPhy_enableState: PHY 19: no supported caps found
[MCU2_0]   1478.887117 s: EnetPhy_enableState: PHY 12: no supported caps found
[MCU2_0]   1478.887410 s: EnetPhy_enableState: PHY 3: no supported caps found
[MCU2_0]   1478.887685 s: EnetPhy_enableState: PHY 18: no supported caps found
[MCU2_0]   1478.888059 s: EnetPhy_enableState: PHY 19: no supported caps found
[MCU2_0]   1478.987116 s: EnetPhy_enableState: PHY 12: no supported caps found
[MCU2_0]   1478.987408 s: EnetPhy_enableState: PHY 3: no supported caps found
[MCU2_0]   1478.987681 s: EnetPhy_enableState: PHY 18: no supported caps found
[MCU2_0]   1478.988048 s: EnetPhy_enableState: PHY 19: no supported caps found
[MCU2_0]   1479.087114 s: EnetPhy_enableState: PHY 12: no supported caps found
[MCU2_0]   1479.087407 s: EnetPhy_enableState: PHY 3: no supported caps found

    We have remove port3 and port8, and using port6 port7 as mac-only port.

static Enet_MacPort gEthAppPorts[] =
{
#if defined(SOC_J721E)
    /* On J721E EVM to use all 8 ports simultaneously, we use below configuration
       RGMII Ports - 1,3,4,8. QSGMII ports - 2,5,6,7 */
    ENET_MAC_PORT_1, /* RGMII */
    //ENET_MAC_PORT_3, /* RGMII */
    ENET_MAC_PORT_4, /* RGMII */
    //ENET_MAC_PORT_8, /* RGMII */
#if defined(ENABLE_QSGMII_PORTS)
    //ENET_MAC_PORT_2, /* QSGMII main */
    //ENET_MAC_PORT_5, /* QSGMII sub */
    ENET_MAC_PORT_6, /* QSGMII sub */
    ENET_MAC_PORT_7, /* QSGMII sub */
#endif
#elif defined(SOC_J784S4)
    ENET_MAC_PORT_1, /* QSGMII main */
    ENET_MAC_PORT_3, /* QSGMII sub */
    ENET_MAC_PORT_4, /* QSGMII sub */
    ENET_MAC_PORT_5, /* QSGMII sub */
#endif
};

      What else can we do to solve this problem?

Best Regards,

Zhang

Hi,

Can you please confirm, is PHY read/write are success or not?
Also, please share the PHY configuration from MacPortCfg details being used.

Also, please enable the "ENETTRACE_DBG" by updating the below from "enet_component.mk" file in ent.