TMDS64EVM: Memory allocation to MSRAM

Kiyomasa Imaizumi

Part Number: TMDS64EVM

Hello TI support team.

I am using the udma_memcpy_interrupt_am64x sample program in CCS.

Regarding udma_memcpy_interrupt.c, the following srcbuf and destbuf are allocated to DDR.

/* Application Buffers */
uint8_t gUdmaTestSrcBuf[UDMA_ALIGN_SIZE(UDMA_TEST_NUM_BYTES)] __attribute__((aligned(UDMA_CACHELINE_ALIGNMENT)));
uint8_t gUdmaTestDestBuf[UDMA_ALIGN_SIZE(UDMA_TEST_NUM_BYTES)] __attribute__((aligned(UDMA_CACHELINE_ALIGNMENT)));

I would like to allocate srcbuf and destbuf to MSRAM, how should I do this?
My purpose is to find out whether there is a difference in DMA transfer speed from DDR to DDR and from MSRAM to MSRAM.

Best reagrds,
Kiyomasa Imaizumi.

over 1 year ago

0 Tushar Thakur over 1 year ago

TI__Mastermind 48958 points

Hello Kiyomasa-san,

Thank you for reaching out to Texas Instruments E2E support forum.

Kiyomasa Imaizumi said:
I am using the udma_memcpy_interrupt_am64x sample program in CCS.

Can you please tell us which version of MCU+SDK are you using?

Also can you please specify, the example is built for which specific core?

Regards,

Tushar

0 Kiyomasa Imaizumi over 1 year ago in reply to Tushar Thakur

Intellectual 760 points

Hello Tushar

Thank you for your reply.

MCU+SDK is mcu_plus_sdk_am64x_08_06_00_45 and using CA53 core sample project.

Regards,

Kiyomasa Imaizumi.

+1 Tushar Thakur over 1 year ago in reply to Kiyomasa Imaizumi

TI__Mastermind 48958 points

Hello Kiyosama,

Thank you for providing the details.

Kiyomasa Imaizumi said:
/* Application Buffers */
uint8_t gUdmaTestSrcBuf[UDMA_ALIGN_SIZE(UDMA_TEST_NUM_BYTES)] __attribute__((aligned(UDMA_CACHELINE_ALIGNMENT)));
uint8_t gUdmaTestDestBuf[UDMA_ALIGN_SIZE(UDMA_TEST_NUM_BYTES)] __attribute__((aligned(UDMA_CACHELINE_ALIGNMENT)));

The above buffer is allocated to *(COMMON) region of the .bss section of memory. To allocate the buffers to MSRAM we need to move the *(COMMON) region to MSRAM memory.

For allocating the above buffers to MSRAM, please change the linker.cmd file with the below provided code.

ENTRY(_c_int00)

__TI_STACK_SIZE = 65536;
__TI_HEAP_SIZE = 131072;

MEMORY
{
    DDR : ORIGIN =  0x80000000, LENGTH = 0x2000000

    MSRAM : ORIGIN = 0x70080000, LENGTH = 0x40000

    /* shared memory segments */
    /* On A53,
     * - make sure there is a MMU entry which maps below regions as non-cache
     */
    USER_SHM_MEM            : ORIGIN = 0x701D0000, LENGTH = 0x80
    LOG_SHM_MEM             : ORIGIN = 0x701D0000 + 0x80, LENGTH = 0x00004000 - 0x80
    RTOS_NORTOS_IPC_SHM_MEM : ORIGIN = 0x701D4000, LENGTH = 0x0000C000
}

SECTIONS {

    .vecs : {} > DDR
    .text : {} > DDR
    .rodata : {} > DDR

    .data : ALIGN (8) {
        __data_load__ = LOADADDR (.data);
        __data_start__ = .;
        *(.data)
        *(.data*)
        . = ALIGN (8);
        __data_end__ = .;
    } > DDR

	.bss.common : {
		*(COMMON)
	} > MSRAM

    /* General purpose user shared memory, used in some examples */
    .bss.user_shared_mem (NOLOAD) : { KEEP(*(.bss.user_shared_mem)) } > USER_SHM_MEM
    /* this is used when Debug log's to shared memory are enabled, else this is not used */
    .bss.log_shared_mem  (NOLOAD) : { KEEP(*(.bss.log_shared_mem)) } > LOG_SHM_MEM
    /* this is used only when IPC RPMessage is enabled, else this is not used */
    .bss.ipc_vring_mem   (NOLOAD) : { KEEP(*(.bss.ipc_vring_mem)) } > RTOS_NORTOS_IPC_SHM_MEM

    .bss : {
        __bss_start__ = .;
        *(.bss)
        *(.bss.*)
        . = ALIGN (8);
        *(COMMON)
        __bss_end__ = .;
        . = ALIGN (8);
    } > DDR

    .heap (NOLOAD) : {
        __heap_start__ = .;
        KEEP(*(.heap))
        . = . + __TI_HEAP_SIZE;
        __heap_end__ = .;
    } > DDR

    .stack (NOLOAD) : ALIGN(16) {
        __TI_STACK_BASE = .;
        KEEP(*(.stack))
        . = . + __TI_STACK_SIZE;
    } > DDR

}

After changing the linker.cmd file, please rebuild the example. Now the buffers will be moved to MSRAM region of the memory.

Please let me know if the above solution helps.

Regards,

Tushar

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TMDS64EVM: Memory allocation to MSRAM