• State TI Thinks Resolved
  • Locked Locked
  • Replies 3 replies
  • Answers 2 answers
  • Subscribers 99 subscribers
  • Views 371 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TDA4VH-Q1: Stackup and Layout for LPDDR

Benjamin
Prodigy 20 points
Part Number: TDA4VH-Q1
  • Can you share details on the EVM detailing the stackup and LPDDR layout that meets the LPDDR channel requirements?
  • Is fly-by routing possible to avoid the impedance change for T-branch routing?
  • Is there any plan to change the implementation for LPDDR to provide 4x LP4s without T-branch routing? (newer or larger part?)
  • 0
    TI__Guru 51695 points

    The PCB stack-up details are provided with the EVM design package (PROC141_STACKUP.PDF).  The EVM's LPDDR4 implementation has been tested/fully validated.

    Fly-by routing is NOT recommended.  The concern regarding the impedance change is understood, but following our guidance to minimize the discontinuity is recommended.

    No plan to support more than one LDDR4 package per interface.  Larger memory density requirements need to be met using more dense devices or stacked die (within single package).

  • 0
    Prodigy 20 points

    Thank You, 

    Do you have a TSA for the EVM's LPDDR4 implementation or other measurements that show it meets JEDEC?

  • 0 in reply to Benjamin
    TI__Guru 51695 points

    No - I don't believe we've captured any LPDDR4 waveforms for TDA4VH-Q1.  We primarily use simulations and testing at process/voltage/temperature corners to verify our solution meets specification.