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16 bit CE1 boot mode problem with C6713B

Good morning,

I have my own board design and my own flash programing code that I use to accept an intel hex file over a serial connector and put it on the flash.  This works perfectly with the 8 bit boot mode but when switching to 16 bit I am having problems.

The first line of the intel hex file is:

:20000000 29000002 2A341802 69C00002 6A000002 76021002 29040002 ABC84002 00000000 38 (spaces to make the diffrent sections clearer)

If i put the file on the flash and power cycle the unit the first section of flash acording to the memory viewer is:

0x90000000 - 02000029 0218342A 0200C069 0200006A 02100276 02000429 0240C8AB 00000000 0200C069

however what has been copied over looks like this:

0x00000000 - 00002929 02020000 34342A2A 02021818 C0C06969 02020000 00006A6A 02020000 02027676 02021010 04042929 02020000 C8C8ABAB 02024040 00000000 00000000

So it seem to be copying over every 8 bit part twice?

When I just load the program to see what the first part should look like this is what I get:

0x00000000 - 02000029 0218342A 0200C069 0200006A 02100276 02000429 0240C8AB 00000000 0200C069

So it seems that what is being put into the flash is correct but the DSP is failing to copy it over correctly.

All that has been changed in the hardware is HD[4:3] to swap to 16 bit boot mode.  The ram its self was always setup in 16 bit mode but only the first 8 bits of each address space was used.

I would very much appericiate any ideas as to what is happening here and how to rectify the problem.

Many thanks

Sean

  • Sean,

    There is nothing obvious that I can think of to cause the complete failure pattern that you have found. From what you describe above, the correct contents have been written to the Flash and can be observed by the DSP through CCS. Also, the correct content can be written to L2 by CCS and observed by the DSP through CCS.

    Sean Bedford said:
    The ram its self was always setup in 16 bit mode but only the first 8 bits of each address space was used.

    Can you add more explanation about this statement, please? I do not understand what it could mean or how it would apply to the Flash boot copy process.

    When you want to debug the results of the bootloading process, it is important to disable the initialization features of the CCS GEL script that may be loaded when you start CCS. The easiest solution is to open CCS without the GEL file, but another option is to edit that GEL file to remove all initialization from the Startup() and On...() functions that run automatically. These functions will change the configuration of the EMIF so you may be observing external memory differently than the DSP observes it while running the bootloader.

    One useful "trick" is to put a B $ / NOP 5 spin instruction pair at the beginning of the code. Of course, that will not work well if the code is not being copied correctly.

    A better method may be to set a hardware breakpoint at 0x00000000 or 0x00000004 to stop the processor immediately after the copy. This might not survive a power cycle, but it might survive a CCS local reset.

    Please let us know what you find.

    Regards,
    RandyP

  • Sorry I meant flash not RAM, as in the configurable option between the flash working in word or byte mode has allways been set to word.

    I have had to go back to 8 bit boot mode for now to continue other development  will try and do as you suggested in the next few days when the current testing on the unit is complete.

    Thank you for the suggestions.

    Sean

  • Good afternoon,

    I did as you said and started it without a gel file and indead the flash did look diffrent.  I have since found a few issues with my code and come up against a brick wall.

    When I change CE1 from 8 bit asych to 16 bit nothing works.  The most sensible explonation I can come up with for this is that the DSP still addresses per byte where as the Flash address per word.

    I think this is what is stopping the commands to the flash working.  The first thing my code does is look if a block is protected this is done by writing 0xAA to 0x555 then 0x55 to 0x2AA then 0x90 to 0x555.  This is followed by a read at 0x2 where the status should be.  If i start in 16bit mode when it comes to the read everything is 0xFFFF (which is what you would expect for an erased block of flash so it isn't undenstanding the commands.  So if I do the first three writes in 8bit mode the flash becomes populated with data.  If at this point i leave it in 8 bit mode it works however if i put it into 16 bit mode by altering the memory location for the CE1 setup it pulls the wrong data out.

    Does this sound like a resonable explanation to you?

    If so is there anything I can do about it other than fudging any flash address that is read to mask it.

    Many thanks

    Sean

  • Sean,

    Let me see if I understand correctly the data signature in your first post. A very important point is that the BOOTMODE pins HD[4:3] are set to 10 for 16-bit half-word EMIF boot, right?

    Sean Bedford said:
    Hex file:
    :20000000 29000002 2A341802 69C00002 6A000002 76021002 29040002 ABC84002 00000000

    Flash through CCS Memory Window:
    0x90000000 - 02000029 0218342A 0200C069 0200006A 02100276 02000429 0240C8AB 00000000

    L2 after the boot 1KB copy:
    0x00000000 - 00002929 02020000 34342A2A 02021818 C0C06969 02020000 00006A6A 02020000

    Is the above the correct understanding of the data observed in that first post? And in that instance, you were observing the Flash and L2 through CCS after the GEL file ran, is that also correct?

    This tells me that your programming code is working correctly, or at least is working the same as the GEL was configuring the EMIF to work.

    Here is what I think we need to know:

    1. What does the "flash did look different" mean? What does the flash looks like in the CCS Memory Window without the GEL?
    2. What Flash device(s) do you have on the EMIF? One x16 Flash or two x8 devices?
    3. To what signals on the Flash device(s) are the control lines connected, esp. EA[4:2] and BE[1:0[?
    4. What other logic do you have between the EMIF and the Flash devices?
    5. Are you really, really sure you have HD[4:3] = 10b? The internal pulls try to put these at 01b.
    6. With the GEL file in use and the Flash appearing correctly in the CCS Memory Window, what is the value of CECTL1, esp. the MTYPE field?
    7. When you power cycle and bring up CCS without the GEL file, what is the value of CECTL1, esp. the MTYPE field?
    8. Try changing MTYPE to 0h and to 1h and see how the Flash appears in those cases.

    Regards,
    RandyP

  • The flash looked diffrent as in it looked the same as what was copied over.  So the 16 bit boot process is clearly working and as I said from this I found a few issues with my code.

    EA[4:2] are connected to A[2:0] on the flash, which is one 16 bit flash chip, BE[1:0] are not connected to the flash. The EMIF is connected directly to the flash and a SRAM chip is also on the bus.  HD[4:3] are deffently at the right levels hence the boot mode is working correctly.

    Now as I said the problem I am having is that the flash stops reponding to commands when I put CE1 in 16 bit mode but works fine when CE1 is in 8 bit mode.  So there is something diffrent about how the two interface when the modes change that stops the flash undernstanding the commands.  Do you have any ideas what this could be?

    As I said the only idea I have had is a problem relating to the flash addressing every 16 bts when the DSP addresses ever byte but not sure how to test for this

    Sean

  • Sean,

    As you can tell, I confuse very easily. Sometimes that is helpful because it makes me ask a lot of questions, and sometimes it frustrates him whom I ask.

    Sean Bedford said:
    The flash looked diffrent as in it looked the same as what was copied over.  So the 16 bit boot process is clearly working and as I said from this I found a few issues with my code.

    The last I heard, the data copied over was in doubled bytes. I would not expect that to change because of the GEL file. So I am confused here.

    Sean Bedford said:
    this is done by writing 0xAA to 0x555 then 0x55 to 0x2AA then 0x90 to 0x555.  This is followed by a read at 0x2 where the status should be.

    Could the problem be that you are using DSP addresses but you should be using Flash addresses? In the EMIF Reference Guide SPRU266, Table 3-2 shows the address translation onto the DSP EA pins. When you read address 0x2 in 8-bit mode, the full byte address A[19:0] (...0010b) is presented on EA[21:2]. When you read address 0x2 in 16-bit mode, the halfword address A[20:1] (...0001b) is presented on EA[21:2]. In 16-bit mode, the address is translated to a halfword address, but the physical value presented to the Flash is the Flash's address and that is what has to be 0x2 or 0x555 or 0x2AA.

    Regards,
    RandyP

     

    If you need more help, please reply back. If this answers the question, please click  Verify Answer  , below.

  • The GEL file was still setting CE1 as 8 bits so only one of the doubled bytes was showing up originally. When set correctly to 16 bit the doubled bytes where also showing up in the flash but this was written while CE1 was mistakenly still set at 8 bits so is probably not very helpful at this stage.

    It does look like you have answered my question though.  I effectivley need to double the addresses in in code that matter for the flash.  I have tested this on the first part of my code and it seems to work so I just need to do it in evey part now.

    Many thanks for pointing me in the right direction