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TDA4AH-Q1: Reference Clock Divider - Valid values

Scott Brown
Prodigy 180 points
Part Number: TDA4AH-Q1
Other Parts Discussed in Thread: TDA4VM

Hi TI,

We are trying to get USXGMII working and are currently debugging to ensure that we are clocked at the correct rate.

In the SDK within csl_serdes3.c (line 408; CSL_serdesRefclkSel), if we want a 156.25MHz reference clock (PMA_CMN_REFCLK_DIG_DIV) the code sets the register to a value of 0x3. However in the J784s4 register spreadsheet, under the wiz16b8m4ct3 tab this is a reserved value. The only appropriate values are 0 and 2, with 3 listed as "Divide by 8 (Reserved)".
Are you able to confirm the code is correct, and the register spreadsheet just hasn't been updated?
Kind regards,
Scott
  • +1
    TI__Mastermind 36930 points

    Hi,

    Scott Brown said:
    In the SDK within csl_serdes3.c (line 408; CSL_serdesRefclkSel), if we want a 156.25MHz reference clock (PMA_CMN_REFCLK_DIG_DIV) the code sets the register to a value of 0x3. However in the J784s4 register spreadsheet, under the wiz16b8m4ct3 tab this is a reserved value. The only appropriate values are 0 and 2, with 3 listed as "Divide by 8 (Reserved)".

    Yes, We are configuring the REFCLK_DIG_DIV to 3 when reference clock is 156.25MHz.
    The same is being used in TDA4VM as well, as SerDes is same.

    Scott Brown said:
    Are you able to confirm the code is correct, and the register spreadsheet just hasn't been updated?

    Code is correct only, might need to update the spreadsheet.


    Can you please confirm the same.

    Best Regards,
    Sudheer

  • +1 in reply to Doredla Sudheer Kumar
    TI__Guru 57810 points

    Sudheer,

    Yes, REFCLK_DIG_DIV is correct at 2b'11.

  • 0
    TI__Guru 57810 points

    Scott,

    what is the issue with the USXGMII? Is there no link up, or no output or the output at the wrong baud rate?

    what is the sdk being used? Is it single lane being used or multilane with multiprotocol?

  • 0 in reply to ShreyasRao
    Prodigy 180 points

    All good now thank you, there was no link up but we determined the problem to be with the other end of the link. After fixing, we now have link-up and have packet tx/rx.

    Thanks for confirming the valid register value.