AM623: Main_SPI0 performance

Shine

Part Number: AM623

Hello Champs,

Customer is using AM623 Main_SPI0 as master , FPGA as slave, through the way of interrupting, can reach 20ms 128*32 byte? Currently, it is planned to directly read and write SPI data via GPIO interrupt and then to the memory via DMA. What is the problem with this scheme? Can we provide some help? For example: How is Main_SPI0 configured for DMA mode, and how can SPI data be read and written via GPIO interrupts?

Below is his requirement.
FPGA is doing ADC sampling, the speed is 20ms 128*32 byte, then give an interrupt to the CPU, the CPU is reading the data of the FPGA in ISR.

Thanks
Regards
Shine

over 1 year ago

0 Vaibhav Kumar over 1 year ago

TI__Mastermind 45486 points

H Shine,

I understand that the customer is using FPGA(Field Programmable Gate Array) as peripheral and AM62x's MAIN_SPI0 as the master.

So currently I can interpret from your question that you want to know how to initiate SPI transfer using GPIO Interrupts. Is my understanding correct ?

Regards,

Vaibhav

0 Shine over 1 year ago in reply to Vaibhav Kumar

TI__Genius 13655 points

Hello Vaibhav,

Thank you very much for your great support.

Yes, customer wants to use GPIO interrupt to trigger SPI, the original scheme was FPGA as host, A-core as slave. Then FPGA sends data to A core, but because there is no slave driver, so A core is used as host, and the FPGA is used as slave. The FPGA gets the ADC data and triggers a GPIO interrupt, A-core receives the interrupt and directly manipulates the SPI read data in ISR.

Thanks
Regards
Shine

0 Vaibhav Kumar over 1 year ago in reply to Shine

TI__Mastermind 45486 points

Hello Shine,

Thanks for the acknowledgement.

Please allow me sometime to comment on this.

Regards,

Vaibhav

0 Vaibhav Kumar over 1 year ago in reply to Shine

TI__Mastermind 45486 points

Hi Shine,

One more follow up question.

So is this Linux centric approach customer is applying or are they using MCU PLUS SDK ?

If its MCU PLUS SDK, I want to know what has the customer used for SoC Initialization as they are many ways to initialize the SoC.

Regards,

Vaibhav

0 Shine over 1 year ago in reply to Vaibhav Kumar

TI__Genius 13655 points

Hello Vaibhav,

Thank you very much.

A core is using Linux.

Because it is too slow to read the spi data through time slice polling, so he wants to use interrupt to read directly, the demand is read spi once per 2ms.

Thanks
Regards
Shine

0 Vaibhav Kumar over 1 year ago in reply to Shine

TI__Mastermind 45486 points

Hi Shine,

I have assigned this question to another expert, please let us know if you do not see any responses in few business days.

Regards,

Vaibhav

0 Shine over 1 year ago in reply to Vaibhav Kumar

TI__Genius 13655 points

Hi Vaibhav,

Okay.

Thank you very much.

Regards
Shine

0 Andreas Dannenberg over 1 year ago in reply to Shine

TI__Guru 69652 points

Shine said:
Customer is using AM623 Main_SPI0 as master , FPGA as slave, through the way of interrupting, can reach 20ms 128*32 byte? Currently, it is planned to directly read and write SPI data via GPIO interrupt and then to the memory via DMA. What is the problem with this scheme? Can we provide some help? For example: How is Main_SPI0 configured for DMA mode, and how can SPI data be read and written via GPIO interrupts?

Reading something from SPI every 20ms in an interrupt-driven way should not be an issue; interrupt response time and context switch times should be in the range of 10s of us (depending on system as well as kernel configuration), leaving plenty of time for processing.

On a high-level here's one way get the data moving from the FPGA to the AM62:

Implement a custom Kernel driver leveraging the Linux IIO framework (https://www.kernel.org/doc/html/latest/driver-api/iio/index.html). It's almost perfectly tailored for this use case, and allows for easy access of the data though a sysfs interface
In the custom driver, use/configure the SPI interface, and use a GPIO-based interrupt scheme. The reading/writing of data from the FPGA over SPI can either be done through SPI framework commands, or the 'regmap' abstraction layer, like many of the existing IIO drivers do.
You can look for and clone an existing SPI-based IIO driver that uses interrupts as a template for a custom driver, such as this one here:
https://git.ti.com/gitweb?p=ti-linux-kernel/ti-linux-kernel.git;a=blob;f=drivers/iio/temperature/ltc2983.c;hb=refs/heads/ti-linux-6.1.y
Then you can also see at the associated device tree bindings to see how the device is configured, and how interrupts are connected, as an example to model after:
https://git.ti.com/gitweb?p=ti-linux-kernel/ti-linux-kernel.git;a=blob;f=Documentation/devicetree/bindings/iio/temperature/adi%2Cltc2983.yaml;h=722781aa4697e46d5f4fa1ca03e48ddf7639ce39;hb=refs/heads/ti-linux-6.1.y#l401

Regards, Andreas

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AM623: Main_SPI0 performance