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AM625: SysConfig DDR changes

Jonathan Cormier
Genius 3851 points
Part Number: AM625
Other Parts Discussed in Thread: SYSCONFIG

I was generating some new DDR4 configs and noticed some unexpected register changes.  Below is the comparison with our existing 2GB module, which matches the EVM.  Could you explain what the changes are?

I looked at the release notes for the sysconfig tool but none of this was mentioned. www.ti.com/.../1.19.0.3426

$ diff ~/local/u-boot-mitysom-62x/arch/arm/dts/k3-am62x-sk-ddr4-1600MTs.dtsi mitysom_am62_2GB_DDR4.dtsi -u
--- /home/jcormier/local/u-boot-mitysom-62x/arch/arm/dts/k3-am62x-sk-ddr4-1600MTs.dtsi  2024-01-25 15:17:50.420051584 -0500
+++ mitysom_am62_2GB_DDR4.dtsi  2024-01-25 15:08:28.848609782 -0500
@@ -1,17 +1,19 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * This file was generated with the
- * AM62x SysConfig DDR Subsystem Register Configuration Tool v0.09.09
- * Fri Oct 27 2023 11:47:38 GMT-0400 (Eastern Daylight Time)
+ * AM62x SysConfig DDR Subsystem Register Configuration Tool v0.10.01
+ * Thu Jan 25 2024 15:04:00 GMT-0500 (Eastern Standard Time)
  * DDR Type: DDR4
  * Frequency = 800MHz (1600MTs)
  * Density: 16Gb
  * Number of Ranks: 1
 */
 
+
 #define DDRSS_PLL_FHS_CNT 6
 #define DDRSS_PLL_FREQUENCY_1 400000000
 #define DDRSS_PLL_FREQUENCY_2 400000000
+#define DDRSS_SDRAM_IDX 15
 
 
 #define DDRSS_CTL_0_DATA 0x00000A00
@@ -608,10 +610,10 @@
 #define DDRSS_PI_168_DATA 0x0000003A
 #define DDRSS_PI_169_DATA 0x0004003A
 #define DDRSS_PI_170_DATA 0x04000400
-#define DDRSS_PI_171_DATA 0xC8040009
+#define DDRSS_PI_171_DATA 0x68040009
 #define DDRSS_PI_172_DATA 0x0400091C
-#define DDRSS_PI_173_DATA 0x00091CC8
-#define DDRSS_PI_174_DATA 0x001CC804
+#define DDRSS_PI_173_DATA 0x00091C68
+#define DDRSS_PI_174_DATA 0x001C6804
 #define DDRSS_PI_175_DATA 0x00000118
 #define DDRSS_PI_176_DATA 0x00001860
 #define DDRSS_PI_177_DATA 0x00000118

  • 0
    TI__Guru* 85990 points

    Jonathan, release notes for the DDR Register Configuration tool specifically will be in the README link at the top of the page in the tool.  That will explain the differences between v0.09.09 and v0.10.01

    Regards,

    James

  • 0 in reply to JJD
    Genius 3851 points

    Thanks for the pointer, I found the change logs but am still confused as to what the changes are for.

    The DDRSS_SDRAM_IDX field isn't mentioned at all.

    The PI_171 change, changes the PI_TPARITY_ERROR_CMD_INHIBIT_F0 field, defined below however there is no mention of parity or inhibit in the release notes.

        Defines the window after the PI receives a parity error during
        which DRAM commands will not execute for frequency set 0.

    The PI_173 change: PI_TPARITY_ERROR_CMD_INHIBIT_F1

    The PI_174 change: PI_TPARITY_ERROR_CMD_INHIBIT_F2

    All the fields seem related but I'm unclear why they were changed.

  • +1 in reply to Jonathan Cormier
    TI__Guru* 85990 points

    Hi Jonathan, the PI_TPARITY_ERROR_CMD_INHIBIT_x  depends on tPAR_ALERT_PWmax, which you specify in the tool.  Is that value by chance different than before in your configuration?

    The DDRSS_SDRAM_IDX field is new and is intended for future revisions of the driver that will use it.  It is the value that is intended for the SDRAM_IDX field in the DDR wrapper register (see below).  This value gives the DDRSS wrapper information on the size of the memory on your board, so it can block unintended addresses and eliminate any memory aliasing.  

     

    Regards,

    James

  • 0 in reply to JJD
    Genius 3851 points
    JJD said:
    Hi Jonathan, the PI_TPARITY_ERROR_CMD_INHIBIT_x  depends on tPAR_ALERT_PWmax, which you specify in the tool.  Is that value by chance different than before in your configuration?

    Thanks, your right. I used the DDR4-1600 settings instead of the DDR4-3200 ones which the SK was using. Reverted my config changes to keep in sync with the evm.

    JJD said:
    The DDRSS_SDRAM_IDX field is new and is intended for future revisions of the driver that will use it.  It is the value that is intended for the SDRAM_IDX field in the DDR wrapper register (see below).  This value gives the DDRSS wrapper information on the size of the memory on your board, so it can block unintended addresses and eliminate any memory aliasing.  

    Okay, I assume the 11h default is enough for 4GB of ram then?  I shouldn't have to tweak it in u-boot 2021?

  • 0 in reply to Jonathan Cormier
    TI__Guru* 85990 points

    Jonathan, yes, anything equal or larger than how SDRAM_IDX is defined will work, but realize that using a larger number won't allow the DDR wrapper to identify aliased addresses.  So if you keep it at 17 (11h), it will think there is an 8GB memory and won't report any memory aliasing in the 8GB range

    Regards,

    James