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DRA829J: PLL, Power and Clock configuration: cross-dependencies

Dmitry Tuykov
Expert 1221 points
Part Number: DRA829J
Other Parts Discussed in Thread: DRA829

Dear TI-Team,

 while working on PLL, Power and Clock configuration for DRA829 some points came out. Could you please clarify the following doubts:

  1. When performing configuration for PLL, Power domains and Clock allocation, is there any order that must be followed?
  2. When Clock allocation is being performed, shall we take into consideration the Power state (corresponding LPSC must be turned On/Off or it’s not relevant)?
  3. When a device is not used and the corresponding LPSC is turned OFF, shall we set the device to reset state (if possible)?

Best regards,
Dmitry

  • 0
    TI__Mastermind 20090 points

    1.) When working with an AVS domain, please set the new voltage before configuring clocks or LPSC domains.
    2.) The PLL can be configured independent of the power domains and LPSCs.
    3.) The power domains cannot be disabled until the LPSCs which comprise the power domain are SWRstDisabled; when powering up, the power domain must come-up first before the LPSC is switched from SWRstDisable to Enable

    SWRstDisable gates clocks to the IP and puts the IP in reset.

    Kevin

  • 0 in reply to Kevin Lavery
    Expert 1221 points

    Hello Kevin,

    Thank you for your answer.

    However, I’d ask you for additional clarification please.

    1. My question is not related with dynamic power management. I want to clarify if during the boot phase, to apply the initial configuration for PLL, PD/LPSC and Clock Source selection (CLK_SEL), shall we follow any specific order or sequence (for example Clock Source selection then PLL and at the end PD/LPSC or something like this)? Mainly to understand if we must respect any precedence.

    2. This question is not directly connected to PLL configuration. The intention is to know whether a LPSC state (On/Off) must be set before changing Clock Source selection (CLK_SEL) for a specific device. For instance, if we want to change a Clock Source for a specific device from once clock to another (e.g. from HFOSC to MAIN_PLL), do we need to take care of the LPSC state prior changing the Clock Source?

    3. For the devices (LPSC) that we do not want to use, which state is recommended “SwRstDisable” or “Disable”?
      What is the difference between of these states?

    4. Is it possible to configure multiple PDs and LPSCs by setting registers PSC0_PDCTL_y[0] NEXT and PSC0_MDCTL_y[4-0] NEXT, and then trigger PSC0_PTSTAT[x] GOSTAT to 1 at once for all made configurations? Al do we need to repeat the sequence for each PD and LPSC?

    Best regards,
    Dmitry

  • 0 in reply to Dmitry Tuykov
    TI__Mastermind 20090 points

    Dmitry,

    (1,2) You should select the clock source before you configure the PLL.
    The PLL can be configured independent of the power domains and LPSCs.

    (3) In SwRstDisable, the IP is reset and clocks are gated; in Disable, the IP is NOT reset BUT the clocks are gated.

    (4) I configure LPSC (MDCTL) and PD (PDCTL) in a single GOSTAT operation. I have never tried this across power domains.

    Kevin