[FAQ] AM625 / AM623 / AM62A Design Recommendations / Commonly Observed Errors during Custom board hardware design – SK Schematics updates for Design Update Note

Hi Board designers, 

Here are some recommended updates based on the learnings for performance improvements.

Schematics - Design Value Updates 

1. VCC_3V3_SYS LOAD SWITCH

SoC IO supply rails have slew rate requirements specified.

Refer Power Supply Slew Rate Requirement section of the data sheet.

Add a cap 220 pF or higher on the Load switch CT (Switch slew rate control) pin.

2. SD card power reset Load switch 

Add a cap 220 pF or higher on the Load switch CT (Switch slew rate control) pin.

3. eMMC supply decap

Add decaps as required to the eMMC memory supply rails 

4. USB VBUS divider 

5. Provision to Bypass CMC

6. USB power switch 

Use power switch with OC indication. Connect the OC output of the power switch to SoC input

5. Caution with EPHY 1V and VPP 1.8V LDO

Miniature DQN package used.

Package Outline

PCB pads 

There is a likely chance of assembly error due to the LOD outline, pins orientation and  the land pattern (pads and pitch)

Regards,

Sreenivasa

Hi Board designers, 

Refer below workarounds when load switch is not used for resetting the SD card power supply and the supply is fixed to 3.3V

https://software-dl.ti.com/processor-sdk-linux/esd/AM62X/09_02_01_09/exports/docs/linux/Foundational_Components/Kernel/Kernel_Drivers/Storage/MMC-SD.html?highlight=mmc#steps-for-working-around-sd-card-issues

https://software-dl.ti.com/processor-sdk-linux/esd/AM64X/latest/exports/docs/linux/Foundational_Components/Kernel/Kernel_Drivers/Storage/MMC-SD.html

Given below are the list of various workarounds that can be done in the device tree node to get SD card working. The workarounds are ordered in increasing order of reducing performance.

All the changes mentioned below, are to be done in the MMCSD device tree node corresponding to the SD instance. This is usually the first (index starting from zero) instance.

1. Restricting to a given speed mode
   • By default the kernel driver tries to enumerate a SD card in the highest supported speed mode. Given below is the order in which the driver tries to enumerate a SD card
     • SDR104
     • DDR50
     • SDR50
     • SD HS
     • SD legacy
   • These speed capabilites can be masked using device tree property sdhci-caps-mask.
     • Limit to DDR50: sdhci-caps-mask= <0x00000002 0x00000000>
     • Limit to SDR50: sdhci-caps-mask= <0x00000006 0x00000000>
     • Limit to SD HS: sdhci-caps-mask= <0x00000007 0x00000000>
     • Limit to SD legacy: sdhci-caps-mask= <0x00000007 0x00200000>

·   &sdhci1 {·       /* SD/MMC */·      vmmc-supply = <&vdd_mmc1>;·      vqmmc-supply = <&vdd_sd_dv>;·      pinctrl-names = "default";·      pinctrl-0 = <&main_mmc1_pins_default>;·      ti,driver-strength-ohm = <50>;·      disable-wp;·      sdhci-caps-mask = <0x00000006 0x00000000>; /* Limiting to SDR50 speed mode */·   };

• Limiting to SD HS speed mode can also be done by using the property no-1-8-v. This disable switching to 1.8V which is required for UHS speed modes(SDR104, DDR50, SDR50)

·   &sdhci1 {·       /* SD/MMC */·       vmmc-supply = <&vdd_mmc1>;·       vqmmc-supply = <&vdd_sd_dv>;·       pinctrl-names = "default";·       pinctrl-0 = <&main_mmc1_pins_default>;·       ti,driver-strength-ohm = <50>;·       disable-wp;·       no-1-8-v; /* disabling all the UHS modes */};

Regards,

Sreenivasa

Hi Board designers, 

Here are some guidelines that needs to be considered when selecting or designing the SOC power architecture

• Power supplies are configured to the required voltage level and are supplies are within the ROC
• Power architecture follows the power-up and power-down sequence as specified in the SOC data sheet
• Power architecture meets the slew rate requirements as specified in the SOC data sheet
• Ensure all the power supplies are available before the MCU_PORz is released
• Monitoring of all the supply rails
• Ensure the supplies are turned ON only after the voltage is below 0.3V (no residual voltage) after a power cycle
• The delay between the power supply ramp and the MCU_PORz high is as per the data sheet recommendations (9.5 ms min)
• The MCU_PORz slew is as minimum as possible to avoid internal reset circuit glitch

Cap_VDDSx
A capacitance in the range 0.8..1.5uF is recommended for the LDO for stability.
This does not include the change in capacitance due to DC bias effect, temperature and ageing.

FET switch for connecting supplies to SOC including VPP supply for eFuse
The SOC IO supplies have slew rate requirements specified.
Refer Power Supply Slew Rate Requirement section of the data sheet.
The VPP supply has a 400 mA load transient current specifiec. the VPP supply is expected to be within the ROC
during programming. FET switch or Load switch supply could dip during power-up and affect the key writing or the SOC operation

Regards,

Sreenivasa

Hi Board designers, 

To implement UHS-I refer below steps:

The SD card interface pullups have to be connected to the 3.3V_1.8V VDDSHV_SDIO switched supply output from the PMIC 

The SD card needs to be powered using a fixed 3.3V supply.

The 3.3V supply to the SD card needs to be switched through a power switch

Provision to reset the power switch using SOC IOs is recommended 

An ANDing logic is recommend to reset the SD cars power switch. 

The SOC VDDSHV5 supply needs to be connected to the .3V_1.8V VDDSHV_SDIO switched supply output from the PMIC

Regards,

Sreenivasa