Power sequencing for C66

A sequencing solution will depend on a number of factors.  The UCD9222 can sequence both the AVS core and fixed core voltages and provides a 'power good' output that can be used to start the sequencing of the other supplies.  Depending on which supplies you choose you may be able to chain the 'power good' signals to the power supply enables with minimal logic to generate the proper sequencing.  The FPGA was used on the EVM for convenience and flexibility of delay values and we are not suggesting that you need one in a final product design.

Hi Bill,

May I know what other alternatives there are to carry out the power sequencing other than using the FPGA?

Currently, I am looking at the UCD90910 or UCD90914 power supply sequencer.
Are those power sequencers a good alternative? Or are there any better power sequencers?

However, the GPIOs and the reset switches are currently handled by the FPGA in the Evaluation Board's example design.
I guess these functions may have to be handled by another device? 

Thanks! 

Hello, I know this is a late response and I don't know your solution but my co-worker just did a C6674 design and he kept things simple. He didn't choose to have the FPGA control the DSP power-sequencing. He used individual regulators that had enable pins and a Schmitt-Trigger Buffer (SN74LVC3G17) to control those enables.  Also, the Smart Reflex was made simple too. But everyone has their own way of doing things and each has pros and cons.

Respectfully,

joe

Hello, just wanted to add some information how the SmartReflex was implemented. Please refer to data sheet: LM10011.

joe

Hello, I'm looking for comments on the best Power-Supply Sequence: Sequence 1 (Core-Before-IO) or Sequency 2 (IO-Before-core)?

Which one is better?

Thanks,

joe