AM69: Memory bus and power consumotion

Taku Murayama

Part Number: AM69

・The current CPU (LS1046A NXP) is 64 bit x 1, but the AM69 series is 32 bit x 4. Will this be degraded compared to the current memory bandwidth?

If we can think of 32-bit x4=128-bit, it seems like an upgrade, but I think so. Also, I would like to know why the memory bus is 32-bit, even though it is a 64-bit core.

・Could you tell me the power consumption for AM69 at the use rate below?

-AM69 (A72x4)

50%:

60%:

70%:

80%:

90%:

100%:

-AM69 (A72x8)

50%:

60%:

70%:

80%:

90%:

100%:

10 months ago

0 Alexey Bagaev 10 months ago

Genius 5495 points

Greetings,

Power estimation spreadsheet for this processor is publicly available https://www.ti.com/lit/zip/sprujb1

AM69 has CortexA72 cores, which are full 64 bit superscalar cores.

The memory is 4x 32-bit multichannel DDR, so it can transfer 2 64 bit words by clock cycle.

But such complicated CPUs don't' address memory directly, but through static multistage caches and MMU.

Hope this can help.

Regards,

Alexey

0 Taku Murayama 10 months ago in reply to Alexey Bagaev

TI__Intellectual 1400 points

Is it possible to use it in 2x32 bit?
When using 2x32bit, does it mean that one 64-bit word can be transferred per clock cycle?

0 Alexey Bagaev 10 months ago in reply to Taku Murayama

Genius 5495 points

Taku,

Using number of DDR channels is based of low level configuration which is responsibility of R5 auxiliary core, when DDR controller is initialized at start-up process. Anyway, data from and to DDR do not go in per-word basis, but rather per page basis, which is linked to transfer static memory cache. So, end result is just theoretical maximum speed of a packet.

Regards...

0 Taku Murayama 10 months ago in reply to Alexey Bagaev

TI__Intellectual 1400 points

Hi Alexey,

Thank you for the answer! Do you mean that the customer can use 2x32 bit, or the customer have to try in their system to confirm?

0 Alexey Bagaev 10 months ago in reply to Taku Murayama

Genius 5495 points

Hi Taku,

I think this depends of number of physical DDR chips installed on a system. If you have 4 chips * 8 GB, using 2 channels lead to 16 GB available of RAM to use, which is impractical. DDR reads and writes 32 bit words from each chip data bus.

Regards...

0 Taku Murayama 10 months ago in reply to Alexey Bagaev

TI__Intellectual 1400 points

Hi Alexey,

Let me clearify. If you are using LPDDR4 32-bit bus chips, do you assume that you have four 8GB (64GB) chips and two 8GB (64GB) chips?

Best regards

0 Alexey Bagaev 10 months ago in reply to Taku Murayama

Genius 5495 points

8 GB * 4 chips = 32 GB. Each chip has 32 bit bus, so 4 (32bit) channels distributed by 4 chips.

0 Alexey Bagaev 10 months ago in reply to Taku Murayama

Genius 5495 points

DDR can send 128 bit word data to all 4 chips by one cycle. But Linux + MMU + DDR decide where to put this data and how. Data send to DDR chip by DDR controller using packets from and to static cache. Linux generate random index tables, so, data randomly distributed by DDR memory and concurrently by many DDR chips. Linux manages reservation of data by each process and thread so by finishing process memory allocation releases indexes to dynamic DDR memory locations. This concept completely different from microcontroller world and have specific abstraction layer to eliminate any technical staff from code.

Regards...

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AM69: Memory bus and power consumotion