TMS320C6657: TMS320C6657: PCIe Cpu transfer: write from endpoint to root complex?

Hi,

The expert is out of office. Please expect delay in responses.

- Keerthy

To my knowledge, bus mastering bit should be configured in end point, so it could write back to RC. Also keep in mind possible translations.

Hi khouloud jendoubi

The following is the content from the readme.txt of a sample PCIE example:-

===========================================================

Sequence / example to test the data transaction between root complex and the endpoint and vice versa

===========================================================

Please note here, the shanon refers to "C6678". But I believe it is the same sequence applicable for C6657 too.

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******************************************************************************
* FILE PURPOSE: Readme File for the PCIE Example Project
******************************************************************************
* FILE NAME: Readme.txt
* Copyright (C) 2011, Texas Instruments, Inc.
*****************************************************************************

The example demonstrates the use of APIs provided in PCIE LLD. This example does NOT work
in the Shannon Simulator.
Check the release notes for pre-requisites, tools and version information.

------------------
Example Overview
------------------

In the PCIe sample example two Shannon EVMs are used to test the PCIe driver. As described in the following figure, Shannon 1 is configured as a Root Complex and Shannon 2 is configured as End Point.

Shannon 1                                 Shannon 2
------------------                            ------------------

| Root        |                PCIe Link    | End Point |
| Complex | <-------------------------->|                 |
------------------                           ------------------

At startup, each EVM configures its PCIe subsystem:
• Serdes, clock, PLL
• PCIe Mode and Power domain
• Inbound/Outbound address translation and BAR registers
• Link training is triggered

Once the PCIe link is established, the following sequence of events will happen:
• Shannon 1 sends data to Shannon 2
• Shannon 2 waits to receive all the data
• Shannon 2 sends the data back to Shannon 1
• Shannon 1 waits to receive all the data
• Shannon 1 verifies if the received data matches the sent data and declares test pass or fail.

-------------------------
Steps to run the example
-------------------------
1. Build the example
2. Do a System Reset in both EVMs
3. Load exampleProject.out in core zero in both EVMs
4. In Shannon 1, use CCS watch window to modify the value of global
variable PcieModeGbl. In this example, Shannon 1 is a Root Complex,
therefore set PcieModeGbl to pcie_RC_MODE (this can be done through a drop down
menu in the watch window).
5. Click the "Run" button in CCS for both EVMs (it is okay to have a few seconds between
the "Run" buttons are clicked in both sides).

-------------------------
Expected result
-------------------------
1. In Shannon 1 CCS console the status of the test will be updated. At the end, the message
"Test passed" is expected.
2. In Shannon 2 CCS console the status of the test will be updated. At the end, the message
"End of test" is expected.

 ====

IF YOU ARE NOT USING THE PDK EXAMPLE, PLEASE COMPARE YOUR CODE WITH THIS EXAMPLE.

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For End point configuration ( pcieRet_e pcieCfgEP(Pcie_Handle handle) )please refer to the source code located at \ti\drv\pcie\example\sample\src\pcie_sample.c

or the example project of PCIE ---- > "PCIE_evmc6657_wSoCFile_C66BiosExampleProject"

Regards

Shankari G