I know Memory Bank can stall the pipeline, so we should avoid it.
Question1:
As the description of TI's datasheet, it won't stall the pipeline, if we access the same bank that in deferent "Block" or say "Memory Space". My question is that :
1)How to obtain the information about "Block" or "Memory Space"?
2)Can I configure my memory into deferent "Block" or "Memory Space" through some directive?
Question2:
There are 4 Banks(Bank0, Bank1, Bank2, Bank3) in each memory space, and 2 bytes per bank for C6000 devices as datasheet of "TMS320C6000 Optimizing Compiler v7.0 User's Guide"(SPRU187Q, 4.5 Avoiding Memory Bank Conflicts With the Assembly Optimizer ).
But I found a contradiction from "4.2.1.3 L2 Memory Banking" in datasheet of "TMS320C64x+ DSP Megamodule Reference Guide"(SPRU871K). It's description about L2 Memory Banking is defferent from SPRU425A. details as followings:
The L2 memory implements two separate memory ports. Each memory port can control one of:
• 4 × 128-bit banks
• 2 × 128-bit banks
• 1 × 256-bit bank
Refer to the device-specific data manual for more information about the banking scheme implemented on a particular device.
The two memory ports may address memory sections which may or may not be contiguous.
I want to know how to understand the defferences between the two datasheet
Is there anyone would give me some promption, or some references document ?
