Can not write at SARAM memory section on TMS320VC5416?

Tung Dang59069

Other Parts Discussed in Thread: TMS320VC5416, CCSTUDIO

Hi friends,

I'm using TMS320VC5416 communicating with Atmega128 via HPI interface. I want to use Atmega to boot-up DSP via HPI interface at enhanced 8 bit HPI mode.

The application (for DSP) is organized in 3 sections: 80h (DARAM), 28000h(SARAM), 38000h(SARAM). Throughout HPI, I can write and read at the DARAM (80h), but I can not write at 28000h and 38000h. Anybody can help me to guess the cause of the failure? Does DSP need any special configurations?

Any help is highly appreciated

Thanks in advanced

TungDH

over 14 years ago

0 Hyun Kim over 14 years ago

TI__Genius 14965 points

hi,

Are you able to access 18000h-1FFFFh (DARMA) as well? You need to control XPC register to access different pages.

Regards,

Hyun

0 Waiser Mehmood over 13 years ago in reply to Hyun Kim

Prodigy 145 points

Hi,

We are also using TMS320VC5416.We are unable to load .out file.Furthermore after loading GEL File,XPC value is not changed.

Here is our GEL file and linker command file.

/****************************************GEL File********************************************./
StartUp()
{
    OnTargetConnect();
}

OnTargetConnect()
{
    GEL_Reset();
   setup_memory_map();
    setup_extended_memory_map();

    reset_cpu( );

    GEL_TextOut("Gel StartUp Complete.\n");
}

setup_memory_map()
{
    /* All memory maps are based on the PMST value of 0xFFE0 */
    GEL_MapOn();
    GEL_MapReset();

   GEL_MapAdd(0x80,0,0x7F80,1,1);   //daram0-3   /* DARAM */
   GEL_MapAdd(0x0,1,0x60,1,1);          /* MMRs */
   GEL_MapAdd(0x60,1,0x7FA0,1,1);//daram0-3       /* DARAM */
   GEL_MapAdd(0x8000,1,0x8000,1,1);   /* DARAM 4-7 */
   GEL_MapAdd( 0x00000u, 2, 0x10000u, 1, 1 ); // IO Space

}

/*--------------------------------------------------------------*/
/* setup_extended_memory_map()                                  */
/* Extended memory map setup                                    */
/*--------------------------------------------------------------*/
setup_extended_memory_map()
{
    /* Turn on the Extended Memory Map */
     GEL_XMDef( 0x0000u, 0x01eu, 1, 0x8000u, 0x7f );
   GEL_XMOn();

    GEL_TextOut("Memory Map.\n");

    GEL_MapAdd( 0x28000u, 0, 0x08000u, 1, 1 ); // SARAM
    GEL_MapAdd( 0x38000u, 0, 0x08000u, 1, 1 ); // SARAM
}

clear_memory_map()
{
    GEL_MapOff();
}

reset_cpu()
{
    /* Set PMST to: OVLY on; DROM on, CLKOUT off */
    #define PMST_VAL        0x7facu

    /* Set wait-state control reg for: 2 wait states, 4 for I/O */
    #define SWWSR_VAL       0x4492u

    /* Set external-banks switch control for: set CONSEC and BH, CLKOUT/=2 */
    #define BSCR_VAL        0xa002u

    PMST = PMST_VAL;

    /*------------------------------------------------------*/
    /* Don't change the wait states, let the application    */
    /* code handle it.                                      */
    /* Note: at power up all wait states will be the        */
    /* maximum (7)                                          */
    /* SWWSR = SWWSR_VAL;                                   */
    /*------------------------------------------------------*/

    BSCR = BSCR_VAL;

    disable_flash();

    reset_peripherals();

    GEL_TextOut("CPU Reset Complete.\n");
}

/*--------------------------------------------------------------*/
/* disable_flash()                                              */
/* Disable Flash and Enable SRAM                                */
/*--------------------------------------------------------------*/
disable_flash()
{
    /* Disable Flash so SRAM is visible */
    *(int*)0x0005@io = 0x40;

    GEL_TextOut("Flash is disabled.\n");
}

/*--------------------------------------------------------------*/
/* reset_peripherals()                                          */
/* Peripheral Reset                                             */
/*--------------------------------------------------------------*/
reset_peripherals()
{
    IFR = 0xFFFFu;
    IFR = 0x0000u;

    reset_dma();
   // reset_mcbsp0();
// reset_mcbsp1();
// reset_mcbsp2();
// reset_timer0();
// reset_gpio();
}

/*--------------------------------------------------------------*/
/* reset_dma()                                                  */
/* DMA Reset                                                    */
/*--------------------------------------------------------------*/
reset_dma()
{
    /* Set Peripheral Control Register Addresses for DEV_RESET */
    #define DMPREC                  0x0054u
    #define DMSA                    0x0055u
    #define DMSDI                   0x0056u

    #define DMA_CH0_DMFSC_SUB_ADDR 0x0003u
    #define DMA_CH1_DMFSC_SUB_ADDR 0x0008u
    #define DMA_CH2_DMFSC_SUB_ADDR 0x000Du
    #define DMA_CH3_DMFSC_SUB_ADDR 0x0012u
    #define DMA_CH4_DMFSC_SUB_ADDR 0x0017u
    #define DMA_CH5_DMFSC_SUB_ADDR 0x001cu

    *(int *)DMPREC = 0;

    *(int *)DMSA = DMA_CH0_DMFSC_SUB_ADDR;
    *(int *)DMSDI = 0;
    *(int *)DMSDI = 0;
    *(int *)DMSA = DMA_CH1_DMFSC_SUB_ADDR;
    *(int *)DMSDI = 0;
    *(int *)DMSDI = 0;
    *(int *)DMSA = DMA_CH2_DMFSC_SUB_ADDR;
    *(int *)DMSDI = 0;
    *(int *)DMSDI = 0;
    *(int *)DMSA = DMA_CH3_DMFSC_SUB_ADDR;
    *(int *)DMSDI = 0;
    *(int *)DMSDI = 0;
    *(int *)DMSA = DMA_CH4_DMFSC_SUB_ADDR;
    *(int *)DMSDI = 0;
    *(int *)DMSDI = 0;
    *(int *)DMSA = DMA_CH2_DMFSC_SUB_ADDR;
    *(int *)DMSDI = 0;
    *(int *)DMSDI = 0;
}

/*--------------------------------------------------------------*/
/* reset_mcbsp0()                                               */
/* MCBSP0 Reset                                                 */
/*--------------------------------------------------------------*/
reset_mcbsp0()
{
    #define MCBSP0_SPSA             0x0038u
    #define MCBSP0_SPSD             0x0039u

    #define MCBSP_SPCR1_SUB_ADDR    0x0000u
    #define MCBSP_SPCR2_SUB_ADDR    0x0001u
    #define MCBSP_SRGR1_SUB_ADDR    0x0006u
    #define MCBSP_SRGR2_SUB_ADDR    0x0007u
    #define MCBSP_MCR1_SUB_ADDR     0x0008u
    #define MCBSP_MCR2_SUB_ADDR     0x0009u
    #define SRGR1_INIT              0x0001u

    *(int *)MCBSP0_SPSA = MCBSP_SPCR1_SUB_ADDR;
    *(int *)MCBSP0_SPSD = 0;
    *(int *)MCBSP0_SPSA = MCBSP_SPCR2_SUB_ADDR;
    *(int *)MCBSP0_SPSD = 0;

    *(int *)MCBSP0_SPSA = MCBSP_SRGR1_SUB_ADDR;
    *(int *)MCBSP0_SPSD = SRGR1_INIT;
    *(int *)MCBSP0_SPSA = MCBSP_SRGR2_SUB_ADDR;
    *(int *)MCBSP0_SPSD = 0;

    *(int *)MCBSP0_SPSA = MCBSP_MCR1_SUB_ADDR;
    *(int *)MCBSP0_SPSD = 0;
    *(int *)MCBSP0_SPSA = MCBSP_MCR2_SUB_ADDR;
    *(int *)MCBSP0_SPSD = 0;
}

/*--------------------------------------------------------------*/
/* reset_mcbsp1()                                               */
/* MCBSP1 Reset                                                 */
/*--------------------------------------------------------------*/
reset_mcbsp1()
{
    #define MCBSP1_SPSA             0x0048u
    #define MCBSP1_SPSD             0x0049u

    #define MCBSP_SPCR1_SUB_ADDR    0x0000u
    #define MCBSP_SPCR2_SUB_ADDR    0x0001u
    #define MCBSP_SRGR1_SUB_ADDR    0x0006u
    #define MCBSP_SRGR2_SUB_ADDR    0x0007u
    #define MCBSP_MCR1_SUB_ADDR     0x0008u
    #define MCBSP_MCR2_SUB_ADDR     0x0009u
    #define SRGR1_INIT              0x0001u

    *(int *)MCBSP1_SPSA = MCBSP_SPCR1_SUB_ADDR;
    *(int *)MCBSP1_SPSD = 0;
    *(int *)MCBSP1_SPSA = MCBSP_SPCR2_SUB_ADDR;
    *(int *)MCBSP1_SPSD = 0;

    *(int *)MCBSP1_SPSA = MCBSP_SRGR1_SUB_ADDR;
    *(int *)MCBSP1_SPSD = SRGR1_INIT;
    *(int *)MCBSP1_SPSA = MCBSP_SRGR2_SUB_ADDR;
    *(int *)MCBSP1_SPSD = 0;

    *(int *)MCBSP1_SPSA = MCBSP_MCR1_SUB_ADDR;
    *(int *)MCBSP1_SPSD = 0;
    *(int *)MCBSP1_SPSA = MCBSP_MCR2_SUB_ADDR;
    *(int *)MCBSP1_SPSD = 0;
}

/*--------------------------------------------------------------*/
/* reset_mcbsp2()                                               */
/* MCBSP2 Reset                                                 */
/*--------------------------------------------------------------*/
reset_mcbsp2()
{
    #define MCBSP2_SPSA             0x0034u
    #define MCBSP2_SPSD             0x0035u

    #define MCBSP_SPCR1_SUB_ADDR    0x0000u
    #define MCBSP_SPCR2_SUB_ADDR    0x0001u
    #define MCBSP_SRGR1_SUB_ADDR    0x0006u
    #define MCBSP_SRGR2_SUB_ADDR    0x0007u
    #define MCBSP_MCR1_SUB_ADDR     0x0008u
    #define MCBSP_MCR2_SUB_ADDR     0x0009u
    #define SRGR1_INIT              0x0001u

    *(int *)MCBSP2_SPSA = MCBSP_SPCR1_SUB_ADDR;
    *(int *)MCBSP2_SPSD = 0;
    *(int *)MCBSP2_SPSA = MCBSP_SPCR2_SUB_ADDR;
    *(int *)MCBSP2_SPSD = 0;

    *(int *)MCBSP2_SPSA = MCBSP_SRGR1_SUB_ADDR;
    *(int *)MCBSP2_SPSD = SRGR1_INIT;
    *(int *)MCBSP2_SPSA = MCBSP_SRGR2_SUB_ADDR;
    *(int *)MCBSP2_SPSD = 0;

    *(int *)MCBSP2_SPSA = MCBSP_MCR1_SUB_ADDR;
    *(int *)MCBSP2_SPSD = 0;
    *(int *)MCBSP2_SPSA = MCBSP_MCR2_SUB_ADDR;
    *(int *)MCBSP2_SPSD = 0;
}

/*--------------------------------------------------------------*/
/* reset_timer0()                                               */
/* Timer0 Reset                                                 */
/*--------------------------------------------------------------*/
reset_timer0()
{
    #define PRD0            0x0025u
    #define TCR0            0x0026u

    #define PRD1            0x0031u
    #define TCR1            0x0032u

    #define TIMER_STOP      0x0010u
    #define TIMER_RESET     0x0020u
    #define PRD_DEFAULT     0xFFFFu

    *(int *)TCR0 = TIMER_STOP;
    *(int *)PRD0 = PRD_DEFAULT;
    *(int *)TCR0 = TIMER_RESET;
}

/*--------------------------------------------------------------*/
/* reset_gpio()                                                 */
/* GPIO Reset                                                   */
/*--------------------------------------------------------------*/
reset_gpio()
{
    #define GPIOCR          0x0010u

    *(int *)GPIOCR = 0;
}

/*--------------------------------------------------------------*/
/* DSK5416 MENU                                                 */
/*--------------------------------------------------------------*/
menuitem "DSK5416 Functions";

hotmenu Reset()
{
    GEL_Reset();
    reset_cpu( );
}

/*--------------------------------------------------------------*/
/* MEMORY MAP MENU                                              */
/*--------------------------------------------------------------*/
menuitem "Memory Map";

hotmenu SetMemoryMap()
{
    setup_memory_map();
}
hotmenu    SetExtendedMemoryMap()
{
    setup_extended_memory_map();
}
hotmenu ClearMemoryMap()
{
    clear_memory_map();
}

/**********************************Linker Command File**************************************************/

-c

-l C:\CCStudio_v3.3\C5400\cgtools\lib\rts_ext.lib

MEMORY
{

    PAGE 0 : PROG :   origin = 38000h length = 7F80h
      PAGE 1 : DATA:    origin = 8000h length = 8000h


}

SECTIONS
{
   .text     : > PROG PAGE 0
   .cinit    : > PROG PAGE 0
   .switch   : > PROG PAGE 0


   .bss           : > DATA   PAGE 1
   .const         : > DATA   PAGE 1
   .sysmem        : > DATA   PAGE 1
    .stack         : > DATA   PAGE 1
}

/*******************************************************************************/

GEL File load successfully. But XPC is not changed to 0x7F after executing this line

GEL_XMDef( 0x0000u, 0x01eu, 1, 0x8000u, 0x7f );

Please let us know if we are doing anything wrong in the GEL file.

Furthermore we are not successful to change the XPC value from memory window option.

We are using CC 3.3 and Ashling Opella XDS560.

Looking for quick response.

Regards,

Rafaqat

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Can not write at SARAM memory section on TMS320VC5416?