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[FAQ] TDA4VM: How to configure RGMII clock delay on J7 devices?

Doredla Sudheer Kumar
Guru 64580 points
Part Number: TDA4VM

How to configure RGMII clock delay on J7 devices?

  • 0
    TI__Guru 64580 points

    One can fulfill the RGMII delay requirement using any of below options.

    1. Configure both Tx & Rx delay at MAC side, if MAC is supported.
    2. Configure both Tx & Rx delay at PHY side, If PHY is supported.
    3. Enable delay from PCB traces while design of Board, in this case no need to enable delay at PHY or MAC.
    4. Configure the Tx delay at MAC side, and Rx delay at PHY side.

    If PHY side Tx delay is enabled then MAC side we need to disable the Tx Delay.

    Linux SDK:
    We can configure the delay in device tree using the “phy-mode” as follows.

    S.No

    Phy-mode

    Description

    1

    rgmii-id

    Reduced Gigabit MII with No Internal Delay on MAC side, and the Delay will be handled by PHY or Schematic trace.

    2

    rgmii-rxid

    Reduced Gigabit MII with Tx Internal Delay on MAC side, and Rx Delay will be handled by PHY or Schematic trace.


    RTOS SDK:
    In RTOS SDK we don’t have the configuration for the RGMII delay in Application. One need to modify the driver as mentioned in below.

    Default configuration in RTOS SDK disables the RGMII Tx delay at MAC side (RGMII_ID_MODE=1) and programmed on the DP83867 PHY side (PHY on TI EVM) through the following registers.

    • Reg addr 0x32 - RGMII Control Register (RGMIICTL)
    • Reg addr 0x86 - RGMII Delay Control Register (RGMIIDCTL)

    If one wants to enable Tx delay at MAC side, above highlighted code in RTOS SDK to be commented.

    Note:
    RGMII Rx delay configuration not supported in any of J7 devices, It should be enabled from PHY or either PCB traces.

  • 0 in reply to Doredla Sudheer Kumar
    TI__Guru 64580 points

    Hi,

    To configure the RGMII delay at the MAC from the device tree, please check below changes available in your SDK.
    If not, please integrate the changes to allow RGMII delay configuration from the MAC side via device tree settings/configuration.

    diff --git a/drivers/phy/ti/phy-gmii-sel.c b/drivers/phy/ti/phy-gmii-sel.c
index 2828f888ad92..b09285ebc019 100644
--- a/drivers/phy/ti/phy-gmii-sel.c
+++ b/drivers/phy/ti/phy-gmii-sel.c
@@ -210,26 +210,36 @@ struct phy_gmii_sel_soc_data phy_gmii_sel_soc_dm814 = {
 
 static const
 struct reg_field phy_gmii_sel_fields_am654[][PHY_GMII_SEL_LAST] = {
-	{ [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x0, 0, 2), },
-	{ [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x4, 0, 2), },
-	{ [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x8, 0, 2), },
-	{ [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0xC, 0, 2), },
-	{ [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x10, 0, 2), },
-	{ [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x14, 0, 2), },
-	{ [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x18, 0, 2), },
-	{ [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x1C, 0, 2), },
+	{ [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x0, 0, 2),
+	  [PHY_GMII_SEL_RGMII_ID_MODE] = REG_FIELD(0x0, 4, 4), },
+	{ [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x4, 0, 2),
+	  [PHY_GMII_SEL_RGMII_ID_MODE] = REG_FIELD(0x4, 4, 4), },
+	{ [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x8, 0, 2),
+	  [PHY_GMII_SEL_RGMII_ID_MODE] = REG_FIELD(0x8, 4, 4), },
+	{ [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0xC, 0, 2),
+	  [PHY_GMII_SEL_RGMII_ID_MODE] = REG_FIELD(0xC, 4, 4), },
+	{ [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x10, 0, 2),
+	  [PHY_GMII_SEL_RGMII_ID_MODE] = REG_FIELD(0x10, 4, 4), },
+	{ [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x14, 0, 2),
+	  [PHY_GMII_SEL_RGMII_ID_MODE] = REG_FIELD(0x14, 4, 4), },
+	{ [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x18, 0, 2),
+	  [PHY_GMII_SEL_RGMII_ID_MODE] = REG_FIELD(0x18, 4, 4), },
+	{ [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x1C, 0, 2),
+	  [PHY_GMII_SEL_RGMII_ID_MODE] = REG_FIELD(0x1C, 4, 4), },
 };
 
 static const
 struct phy_gmii_sel_soc_data phy_gmii_sel_soc_am654 = {
 	.use_of_data = true,
 	.regfields = phy_gmii_sel_fields_am654,
+	.features = BIT(PHY_GMII_SEL_RGMII_ID_MODE),
 };
 
 static const
 struct phy_gmii_sel_soc_data phy_gmii_sel_cpsw5g_soc_j7200 = {
 	.use_of_data = true,
 	.regfields = phy_gmii_sel_fields_am654,
+	.features = BIT(PHY_GMII_SEL_RGMII_ID_MODE),
 	.extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII) | BIT(PHY_INTERFACE_MODE_SGMII),
 	.num_ports = 4,
 	.num_qsgmii_main_ports = 1,
@@ -239,6 +249,7 @@ static const
 struct phy_gmii_sel_soc_data phy_gmii_sel_cpsw9g_soc_j721e = {
 	.use_of_data = true,
 	.regfields = phy_gmii_sel_fields_am654,
+	.features = BIT(PHY_GMII_SEL_RGMII_ID_MODE),
 	.extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII) | BIT(PHY_INTERFACE_MODE_SGMII),
 	.num_ports = 8,
 	.num_qsgmii_main_ports = 2,
@@ -248,6 +259,7 @@ static const
 struct phy_gmii_sel_soc_data phy_gmii_sel_cpsw9g_soc_j784s4 = {
 	.use_of_data = true,
 	.regfields = phy_gmii_sel_fields_am654,
+	.features = BIT(PHY_GMII_SEL_RGMII_ID_MODE),
 	.extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII) |
 		       BIT(PHY_INTERFACE_MODE_USXGMII),
 	.num_ports = 8,