Part Number: AM5718
Hi TI experts!
We are sharing a region of DDR where IPU1 (TI-RTOS) writes some positions and some linux binaries (A15) read from it. This region of DDR was originally declared as CMEM into the DTB but we are not using it as CMEM because multiple binaries will need to have access to the very same region in our application, so these binaries actually use open + mmap with MAP_SHARED flag.
We've seen that, sometimes, Linux-A15 cache prefetchs memory positions that haven't been written yet so when the proper time to read these positions arrives, the binary gets the information from the cache with incorrect data (checked with a pattern of invalid data) instead of reading it directly from memory (Yes, we are using volatile variables, but cache goes beyond them).
Could you provide us with a way to tell the kernel that a specific region of memory is not cacheable? Additionally, any way to invalidate cache for a specific buffer? We are using Processor SDK 8.02.01
Thank you in advance
Best regards
Roberto
