Part Number: AM6442
Other Parts Discussed in Thread: TMDS64EVM
I am working on PCB layout for our new design using the AM64x. I have encountered some challenges related to DDR4, and have a few questions:
1. According to the TI AM64x DDR design and layout guidelines document, the target single ended impedance is 40 ohm. In other designs we have done with other processors, this number is 50 ohm. And the Micron documentation also states the target should be 50 ohm. There are some difficulties routing at 40 ohm since the PCB traces need to be quite a bit wider. Does it have to be 40, or is 50 ohm ok?
2. I was going to copy the DDR4 layout from one of the eval boards, the TMDS64EVM. But it looks like some of the data lines are swapped to make routing easier. The design guide states that this is allowed, but not when using CRC. Will ECC still work in this case, or does this also mean ECC also can’t be used if data bits are swapped?
3. When using LPDDR4, the design guide states that data lines cannot be swapped. Just out of curiosity, what is the difference between DDR4 and LPDDR4 that causes this?
4. Are there any other eval boards or reference designs that have Gerber files for DDR4 routing?
Thanks