Hi,
I would like to ask a question on VPBE's PCR, Peripheral Control Register.
Bit 0 is CLK_OFF, which is described as being able to gate the VPBE module when it is not in use for power saving. However, I found that setting this bit to 1 has no effect on bit operation: LCD still has active data, VSYNC, HSYNC, Enable, DCLK signal, which should be sufficient to indicate that the VPBE has not been gated off.
So why changing this bit is not effective? Could anyone explain this?
Zheng