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AM62A3: am62a models check error

yang yong
Prodigy 130 points
Part Number: AM62A3

When using the PC_dsp_test_dl_algo.out executable file in the AM62A SDK 9.0.1 project, you encountered the following error.

Fullscreen 2781.log.txt Download 
root@21ca7013e986:/home/root/ti-processor-sdk-rtos-j721e-evm-09_01_00_06/c7x-mma-tidl/ti_dl/test# ./PC_dsp_test_dl_algo.out 
----tidlMain-----797----------
----tidlMain-----810----------
----tidlMain-----851----------
----tidlMain-----869----------
----tidlMain-----884----------
----tidlMultiInstanceTest-----268----------
----tidlMultiInstanceTest-----304----------

Processing config file #0 : testvecs/config/infer/public/caffe/tidl_infer_mobilenetV1.txt 
----tidlMultiInstanceTest-----383----------
----tidlMultiInstanceTest-----408------:testvecs/config/tidl_models/caffe/tidl_io_mobilenet_v1_1.bin----
----tidlMultiInstanceTest-----414----------
----tidlMultiInstanceTest-----496----------
----tidlMultiInstanceTest-----516----------
----tidlMultiInstanceTest-----537----------
---------1016----------
----TIDLRT_create-----1043----------
----TIDLRT_create-----1045----------
----TIDLRT_create-----1077----------
----TIDLRT_create-----1088----------
----TIDLRT_create-----1091----------
----TIDLRT_create-----1093----------
TIDL_initDebugTraceParams Done 

--------------------------------------------
TIDL Memory size requiement (record wise):
MemRecNum   , Space               , Attribute   , Alignment   , Size(KBytes), BasePtr     
0           , DDR Cacheable       , Persistent  ,  128, 15.25   , 0x00000000
1           , DDR Cacheable       , Persistent  ,  128, 0.64    , 0x00000000
2           , DDR Cacheable       , Scratch     ,  128, 16.00   , 0x00000000
3           , DDR Cacheable       , Scratch     ,  128, 448.00  , 0x00000000
4           , DDR Cacheable       , Scratch     ,  128, 2944.00 , 0x00000000
5           , DDR Cacheable       , Persistent  ,  128, 4743.91 , 0x00000000
6           , DDR Cacheable       , Scratch     ,  128, 7.75    , 0x00000000
7           , DDR Cacheable       , Scratch     ,  128, 148.25  , 0x00000000
8           , DDR Cacheable       , Scratch     ,  128, 4728.12 , 0x00000000
9           , DDR Cacheable       , Scratch     ,  128, 1579.00 , 0x00000000
10          , DDR Cacheable       , Persistent  ,  128, 447.48  , 0x00000000
11          , DDR Cacheable       , Scratch     ,  128, 512.25  , 0x00000000
12          , DDR Cacheable       , Persistent  ,  128, 0.12    , 0x00000000
13          , DDR Cacheable       , Persistent  ,  128, 7069.64 , 0x00000000
14          , DDR Cacheable       , Persistent  ,  128, 0.03    , 0x00000000
--------------------------------------------
Total memory size requirement (space wise):
Mem Space , Size(KBytes)
DDR Cacheable, 22660.45
--------------------------------------------
NOTE: Memory requirement in host emulation can be different from the same on EVM
      To get the actual TIDL memory requirement make sure to run on EVM with 
      debugTraceLevel = 2

--------------------------------------------
----TIDLRT_create-----1097----------
----TIDLRT_create-----1107----------
----TIDLRT_create-----1125----------
----TIDLRT_create-----1138----------
TIDL init call from ivision API 

--------------------------------------------
TIDL Memory size requiement (record wise):
MemRecNum   , Space               , Attribute   , Alignment   , Size(KBytes), BasePtr     
0           , DDR Cacheable       , Persistent  ,  128, 15.25   , 0x7512bd80
1           , DDR Cacheable       , Persistent  ,  128, 0.64    , 0x7512ae00
2           , DDR Cacheable       , Scratch     ,  128, 16.00   , 0x79bf3080
3           , DDR Cacheable       , Scratch     ,  128, 448.00  , 0x79bf7080
4           , DDR Cacheable       , Scratch     ,  128, 2944.00 , 0x79c67080
5           , DDR Cacheable       , Persistent  ,  128, 4743.91 , 0x79068080
6           , DDR Cacheable       , Scratch     ,  128, 7.75    , 0x79f47080
7           , DDR Cacheable       , Scratch     ,  128, 148.25  , 0x79f48f80
8           , DDR Cacheable       , Scratch     ,  128, 4728.12 , 0x79f6e080
9           , DDR Cacheable       , Scratch     ,  128, 1579.00 , 0x7a40c100
10          , DDR Cacheable       , Persistent  ,  128, 447.48  , 0x78ff8080
11          , DDR Cacheable       , Scratch     ,  128, 512.25  , 0x7a596d00
12          , DDR Cacheable       , Persistent  ,  128, 0.12    , 0x7512fb00
13          , DDR Cacheable       , Persistent  ,  128, 7069.64 , 0x78910080
14          , DDR Cacheable       , Persistent  ,  128, 0.03    , 0x7512fc80
--------------------------------------------
Total memory size requirement (space wise):
Mem Space , Size(KBytes)
DDR Cacheable, 22660.45
--------------------------------------------
NOTE: Memory requirement in host emulation can be different from the same on EVM
      To get the actual TIDL memory requirement make sure to run on EVM with 
      debugTraceLevel = 2

--------------------------------------------
Algorithm Init failed with error number: -1130
----tidlMultiInstanceTest-----539----------
Error at line:   545 : in file /home/root/ti-processor-sdk-rtos-j721e-evm-09_01_00_06/c7x-mma-tidl/ti_dl/test/src/pc_linux/../tidl_tb.c, of function : tidlMultiInstanceTest 
Invalid Error Type!
----tidlMultiInstanceTest-----568----------
----tidlMultiInstanceTest-----592----------
----tidlMultiInstanceTest-----594----------
----tidlMultiInstanceTest-----268----------
----tidlMultiInstanceTest-----304----------

Processing config file #1 :  
Couldn't open Parameter Config file .
Parser Failed----tidlMultiInstanceTest-----592----------
----tidlMultiInstanceTest-----594----------
----tidlMultiInstanceTest-----268----------
----tidlMultiInstanceTest-----304----------

Processing config file #2 :  
Couldn't open Parameter Config file .
Parser Failed----tidlMultiInstanceTest-----592----------
----tidlMultiInstanceTest-----594----------

  • 0
    Prodigy 130 points

    Fullscreen tidl_import_mobilenet_v1.txt Download 
    modelType          = 0
inputNetFile       = "../../test/testvecs/models/public/caffe/mobileNet1.0v1/mobilenet_deploy.prototxt"
inputParamsFile    = "../../test/testvecs/models/public/caffe/mobileNet1.0v1/mobilenet.caffemodel"
outputNetFile      = "../../test/testvecs/config/tidl_models/caffe/tidl_net_mobilenet_v1.bin"
outputParamsFile   = "../../test/testvecs/config/tidl_models/caffe/tidl_io_mobilenet_v1_"
inDataNorm  = 1
inMean = 103.94 116.78 123.68
inScale = 0.017 0.017 0.017
inDataFormat = 0
resizeWidth = 256
resizeHeight = 256
inWidth  = 224
inHeight = 224 
inNumChannels = 3
#numFrames = 1
perfSimConfig = ../../test/testvecs/config/import/device_config.cfg
inData = ../../test/testvecs/config/imageNet_sample_val.txt
postProcType = 1
quantRangeExpansionFactor = 1.5
    Fullscreen tidl_infer_mobilenetV1.txt Download 
    inFileFormat    = 2
postProcType = 1
numFrames   = 1
netBinFile      = "testvecs/config/tidl_models/caffe/tidl_net_mobilenet_v1.bin"
ioConfigFile   = "testvecs/config/tidl_models/caffe/tidl_io_mobilenet_v1_1.bin"
outData =   testvecs/output/airshow_mobileNetv1.bin
inData  =   testvecs/config/classification_list.txt
quantRangeExpansionFactor = 1.0
quantRangeUpdateFactor = 0.0
#inFileFormat    = 3
#inData  =   testvecs/input/0000_3_224x224_paded.y
writeBinsAsHeader = 0
debugTraceLevel = 0
writeTraceLevel = 0
#writeOutput = 0

    Above is my configuration file.

    Operating environment using Docker Ubuntu22.04.

  • 0 in reply to yang yong
    TI__Expert 7385 points

    Hi,

    Thank you for your query.

    I have forwarded your query to our domain expert, they will get back to you.

    Regards,

    Nitika

  • 0 in reply to Nitika Verma
    Prodigy 130 points

    In my case, when the TIDL_init function in the tidl_alg.c file calls the TIDL_OTFPadErrorCheck function, the return value of status is -1130. However, I cannot trace further into the internals.

  • 0 in reply to yang yong
    TI__Expert 4640 points

    Hi Yan Yong, 

    We will be happy to help with your question. To further assist you, would you please provide more context of what you are trying to achieve? 

    Best regards,

    Qutaiba