AM6442: Cortex R5F Performance

Hi Andrean,

Thanks for your query.

Andrean С. said:

The same math computation takes:

Can you provide more info what exactly you are trying here ?

for example:

Which memory location the data and code is stored ?

Method of accessing data ?

Best Regards

Ashwani

Hello Ashwani,

We implement a multi-axis motion control. There are trigonometrical functions, IIR filters, multiplications, divisions and the like. For computation, we only use the "float" type.

The code and data are stored in DDR RAM. We use random memory access to all the data(arrays). The application runs with FreeRTOS.

Best regards,

Andrean

Hello Ming,

Thanks for the fast answer!

We use DDR, but data and instructions are cached. We've just run the same tests with a disabled cache. It takes 3ms(instead of 215uS) to compute the same motion on R5F. We also tried to put data and code into TCM memory. R5f performs the same way as in DDR with an enabled cache.

Is there anything else that could help to improve the performance of the R5 core?

Best regards, 

Andrean

Hi Andrean С,

Can you please share or check linker.cmd file and sysconfig file settings for memory regions ?

Here are some guidelines:

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1236505/faq-am64x-profinet-component-placement-recommendation-for-sitara-mpu-memory

Best Regards

Ashwani

Hello Ashwani,

This is the linker file:

 /* This is the stack that is used by code running within main()
  * In case of NORTOS,
  * - This means all the code outside of ISR uses this stack
  * In case of FreeRTOS
  * - This means all the code until vTaskStartScheduler() is called in main()
  *   uses this stack.
  * - After vTaskStartScheduler() each task created in FreeRTOS has its own stack
  */

 --stack_size=8192
/* This is the heap size for malloc() API in NORTOS and FreeRTOS
* This is also the heap used by pvPortMalloc in FreeRTOS
*/
 --heap_size=200000
-e_vectors  /* This is the entry of the application, _vector MUST be placed starting address 0x0 */

/* This is the size of stack when R5 is in IRQ mode
 * In NORTOS,
 * - Here interrupt nesting is enabled
 * - This is the stack used by ISRs registered as type IRQ
 * In FreeRTOS,
 * - Here interrupt nesting is enabled
 * - This is stack that is used initally when a IRQ is received
 * - But then the mode is switched to SVC mode and SVC stack is used for all user ISR callbacks
 * - Hence in FreeRTOS, IRQ stack size is less and SVC stack size is more
 */
__IRQ_STACK_SIZE = 256;
/* This is the size of stack when R5 is in IRQ mode
 * - In both NORTOS and FreeRTOS nesting is disabled for FIQ
 */
__FIQ_STACK_SIZE = 256;
__SVC_STACK_SIZE = 4096; /* This is the size of stack when R5 is in SVC mode */
__ABORT_STACK_SIZE = 256;  /* This is the size of stack when R5 is in ABORT mode */
__UNDEFINED_STACK_SIZE = 256;  /* This is the size of stack when R5 is in UNDEF mode */



SECTIONS
{
    .vectors  : {
    } > R5F_VECS   , palign(8) 


    GROUP  :   {
    .text.hwi : {
    } palign(8)
    .text.cache : {
    } palign(8)
    .text.mpu : {
    } palign(8)
    .text.boot : {
    } palign(8)
    .text:abort : {
    } palign(8)
    } > MSRAM  


    GROUP  :   {
    .text : {
    } palign(8)
    .rodata : {
    } palign(8)
    } > DDR  


    GROUP  :   {
    .data : {
    } palign(8)
    } > DDR  


    GROUP  :   {
    .bss : {
    } palign(8)
    RUN_START(__BSS_START)
    RUN_END(__BSS_END)
    .sysmem : {
    } palign(8)
    .stack : {
    } palign(8)
    } > DDR  


    GROUP  :   {
    .irqstack : {
        . = . + __IRQ_STACK_SIZE;
    } align(8)
    RUN_START(__IRQ_STACK_START)
    RUN_END(__IRQ_STACK_END)
    .fiqstack : {
        . = . + __FIQ_STACK_SIZE;
    } align(8)
    RUN_START(__FIQ_STACK_START)
    RUN_END(__FIQ_STACK_END)
    .svcstack : {
        . = . + __SVC_STACK_SIZE;
    } align(8)
    RUN_START(__SVC_STACK_START)
    RUN_END(__SVC_STACK_END)
    .abortstack : {
        . = . + __ABORT_STACK_SIZE;
    } align(8)
    RUN_START(__ABORT_STACK_START)
    RUN_END(__ABORT_STACK_END)
    .undefinedstack : {
        . = . + __UNDEFINED_STACK_SIZE;
    } align(8)
    RUN_START(__UNDEFINED_STACK_START)
    RUN_END(__UNDEFINED_STACK_END)
    } > MSRAM  


    GROUP  :   {
    .ARM.exidx : {
    } palign(8)
    .init_array : {
    } palign(8)
    .fini_array : {
    } palign(8)
    } > MSRAM  

    .bss.user_shared_mem (NOLOAD) : {
    } > USER_SHM_MEM    

    .bss.log_shared_mem (NOLOAD) : {
    } > LOG_SHM_MEM    

    .bss.ipc_vring_mem (NOLOAD) : {
    } > RTOS_NORTOS_IPC_SHM_MEM    

    .bss.nocache (NOLOAD) : {
    } > NON_CACHE_MEM    


    GROUP  :   {
    motion : {
    } align(8)
    } > R5F_TCMB0  


}


MEMORY
{
    R5F_VECS   : ORIGIN = 0x0 , LENGTH = 0x40 
    R5F_TCMA   : ORIGIN = 0x40 , LENGTH = 0x7FC0 
    R5F_TCMB0   : ORIGIN = 0x41010000 , LENGTH = 0x8000 
    NON_CACHE_MEM   : ORIGIN = 0x70060000 , LENGTH = 0x8000 
    MSRAM   : ORIGIN = 0x70080000 , LENGTH = 0x40000 
    USER_SHM_MEM   : ORIGIN = 0x701D0000 , LENGTH = 0x80 
    LOG_SHM_MEM   : ORIGIN = 0x701D0080 , LENGTH = 0x3F80 
    RTOS_NORTOS_IPC_SHM_MEM   : ORIGIN = 0x701D4000 , LENGTH = 0xC000 
    FLASH   : ORIGIN = 0x60100000 , LENGTH = 0x80000 
    DDR   : ORIGIN = 0x80000000 , LENGTH = 0x1F0000 

    /* For memory Regions not defined in this core but shared by other cores with the current core */


}

This is the MPU configuration:

Best regards,

Andrean

Hi Andrean,

Thanks for logs.

Can you please share generated memory_map file as well?

Best Regards

Ashwani

Hello Ashwani,

Yes, sure.

Best regards,

Andrean

Thanks Andrean,

Allow me some time to review and get back to you.

Best Regards

Ashwani

Hello Ashwani,

Did you have time to review my files?

Best regards,

Andrean

Hi Andrean С,

Sorry for delay in response.

I am still discussing this internally.

Please allow me some more time.

Thanks for having patience.

Best Regards

Ashwani