about tms320vc33

Hi,

This product is not recommended for new designs. However, the device, tool, or software continues to be in production to support existing customers. TI does not recommend using this part in a new design. TI encourages designers to consider alternative products for new designs.

If your interested in flaoting point DSP's please consider using the new C66x family. E.g. the single core TMS320C6671.

Kind regards,

one and zero

Thank you very much!

Dear TI engineer,

We are going to use TMS320VC33 to replace TMS320C31 on existing products. The reason to use TMS320VC33, rather than C6748/6727 is that the code for TMS320C31 can be directly used in TMS320VC33 without modification, according to TI technical note. Of cause, the hardware has to be modified.

The clock structure in TMS320VC33 is different from that of TMS320C31. There are clock mode selection future in TMS320VC33, defined by I/O pin CLKMD0 and CLKMD1. In our application, the 50MHz clock is from external source which synchronizes with other clocks (for ex, FPGA and power PC). The 50MHz will be fed through EXTCLK pin.

In this case, how to define the clock mode selection, CLKMD0 and CLKMD1? I suppose it should be CLKMD0 = 0 and CLKMD1 = 0. On the page 12 of TMS320VC33 datasheet, it is not clear how to define the clock mode when external clock used.

In addition, there is new feature in TMSVC33, enable interrupt t edge mode selection which is defined by EDGEMODE pin. To keep the original interrupt level sensitive feature in TMS320C31, do you think  EDGEMODE pin should be tied to 0V?

Many thanks for your consideration.

Regards

Han