AM623: U-boot 2023.04 is running speed grade I (1.0Ghz) part at 1.25Ghz

I started trying to get the R5 SPL to change the cpu frequency but this code causes u-boot to hang when it goes to switch to the A53.  Even if I commented out everything but the first fdt_path_offset, it wouldn't boot.  I've run out of time to look into this so for now we are going to limit all our SOMs to 1Ghz while in u-boot.  This didn't impact boot time, which is a bit surprising.

am625_init.c:

/**
 * Reduce A53 frequency for lower speed grades in u-boot dts
 */
static int fixup_cpu_freq(void *fdt_blob)
{
	int ret = 0;
	int nodeoffset, cnt;
	u32 assigned_clk_rates[2];

	nodeoffset = fdt_path_offset(fdt_blob, "/a53@0");
	if (nodeoffset < 0) {
		panic("%s: Could not find /a53@0 node\n", __func__);
		return nodeoffset;
	}

	cnt = fdtdec_get_int_array_count(fdt_blob, nodeoffset,
					 "assigned-clock-rates", assigned_clk_rates,
					 ARRAY_SIZE(assigned_clk_rates));
	// printf("cnt: %d\n", cnt);
	if (cnt < 0) {
		panic("%s: Could not get assigned-clock-rates for /a53@0 node\n",
		       __func__);
		return cnt;
	}
	if (cnt != 2) {
		panic("%s: assigned-clock-rates for /a53@0 node has invalid count %d\n",
		       __func__, cnt);
		return -EINVAL;
	}

	assigned_clk_rates[1] = 1000000000;
	printf("%s: assigned-clock-rates[0] = %u, assigned-clock-rates[1] = %u\n",
	       __func__, assigned_clk_rates[0], assigned_clk_rates[1]);

	ret = fdt_setprop(fdt_blob, nodeoffset, "assigned-clock-rates",
			  assigned_clk_rates, sizeof(assigned_clk_rates));
	if (ret < 0)
		panic("Failed to set assigned-clock-rates property: %d\n", ret);

	return ret;
}

int fdtdec_board_setup(const void *fdt_blob)
{
	return fixup_cpu_freq((void *)fdt_blob);
}