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TDA4VH-Q1: OSPI interface

Bruno B
Expert 1290 points
Part Number: TDA4VH-Q1

Hi,

THe datasheet gives some layout constraints relative to processor to OSPi flash interconnect (external LBCLKO to DQS loopback).

I understand that this intends to mimic the global forward + reverse electrical delay.which can be very necessary when reading at high speed burst.

1) I am wondering how this works when reading a single byte from a QSPI flash. How the Flash access time is taken into account ?

2) How should be calculated the external loopback length when the processor-to-flash interconnection is not direct but through some logic ( eg buffers, or FPGA) ?

3) I could not find where we could set the SPI clock frequency value.  What are the lower and upper limits ?

With best regards,

Bruno

  • +1
    TI__Expert 3040 points

    Hi Bruno,

    Sorry for the delay, returning from the holiday weekend. Working with my team and will follow up shortly.

    Best Regards,

    Matt

  • +1 in reply to Matt Park
    TI__Guru 51695 points

    1. The OSPI interface can operate in 3 different configurations:

    A. Open (no DQS support).  This is a legacy mode and supports the lowest bus frequencies.

    B. Loopback (LBCLKO to DQS).  This mode generates can operate a higher frequencies compared to no DQS support, as read timing has compensation for the propagation delay to/from the memory. 

    C.  DQS Support (DQS to DQS).  This mode the flash memory generates a data strobe (DQS) that can be aligned with data.  This configuration can compensate for propagation delay to/from the memory as well as some flash access timing.  This configuration can operate at highest frequency.

    2.  If the LBCLKO to DQS connection includes the additional delay (buffer) then it could be accounted for in the read timing.

    3.  The data manual (DM) includes the OSPI timing information including CLK cycle time for SDR and DDR modes.