AM6412: PCIe link down issue

Hello Koichiro,

Could you please confirm if your query is in the context of Processor SDK? If yes, I will assign the thread to respective expert.

Regards,

Prashant

Hi Prashant,

The customer is using Linux SDK, but we are not sure the issue is related to software(SDK) or hardware(board, etc.).

Thanks and regards,
Koichiro Tashiro

Hi Koichiro,

Thanks for the context. I have assigned the thread to PCIe PSDK expert for now & notified the PCIe hardware expert as well.

Please confirm that the link operates normally outside this FW update process?

Hi DK,

-DK- said:

Please confirm that the link operates normally outside this FW update process?

Are you asking if PCIe is works fine outside of the FW update process? If so, the answer is yes.

The customer got PCIe eye patterns.
The link down issue happens with both Gen2 and Gen1 modes.

Gen2 (5Gbps) mode:

Gen1 (2.5Gbps) mode:

The customer originally uses Gen2, but based on these eye pattern they are planning to use Gen1 mode.
They are asking how to improve signal quality in Gen1 mode and minimize above red parts.
Are there any methods?

Thanks and regards,
Koichiro Tashiro

These eye diagram excursions are a result of signal integrity issues on the board itself. Please refer to SPRAAR7 and ensure that all recommendations and requirements contained therein have been implemented in your design.

I would recommend that you start with Table A-6. It would also be interesting to see the results of your interface simulation.

Hi DK,

The customer checked the document and found impedance control 95Ohm +/-5% is not met.
(the board was designed with 100Ohm +/- 10%) 
Other parameters are met.
Is this the cause of the issue? 

-DK- said:

It would also be interesting to see the results of your interface simulation.

They did not try the simulation as IBIS model of attached device is not available.

They did some investigation using PCIe analyzer.
Gen1 TX line:


Gen1 RX line:


Q1) Do you find any problem in these analyzer results?
For example, L2 is not supported in the device.

The customer checked errors detected in the analyzer on "OK board" and "Not-OK board".
OK board (left side) :no PCIe link down is observed.
Not-OK board (right side): PCIe link down happens.

As you can see there are many errors.
Errors surrounded with green lines are common for both boards.
Errors surrounded with red lines are unique on Not-OK board.



Q2) Among these errors, do you see suspicious error(s) which may be related to link down?

Thanks and regards,
Koichiro Tashiro

I got detailed analyzer errors.
analyzer errors.xlsx

Hello,

Q1A) The impedance control gap is highly problematic. It very well could be root cause.

The AM64 utilizes a SerDes that was designed to support several high-speed interfaces (USB3, SGMII, PCIe, etc.) rather than one specific interface so the SerDes Tx/Rx impedance was designed to target a range of commonality in terms of specified impedance overlap. In other words, it cannot support the full range of all of these specifications, but can support a much smaller range that is compliant among them. Because of this it is critical that the channel be designed accordingly as there is less margin available than there might be a for a per-interface design. Even with this AM64-specific design decision, I would point out that 100 Ohms +/- 10% violates the base PCIe standard of 68-105 Ohms for GEN2 interfaces so I suspect it presents a problem to both Root Complex and Endpoint in this case.

Q2A) Both the attached XLS and the error outlines referenced in Q2 point to signal integrity issues. I would submit that both "OK" and NOT-OK" results are poor and even the "OK" version is very marginal.

1) If you would like to provide full analyzer traces for these I can review them and (very likely) provide additional evidence, but a channel simulation would provide a more complete picture.

2) Was this schematic reviewed by TI? If so, please provide review ID#. If not, please attach a complete, searchable, PDF of it and I will review the PCIe portion(s).

Hi DK,

I shared you full analyzer logs with TI Drive.
The schematics was reviewed by TI, but I do not know review ID#. I also sent updated schematics offline.

Thanks and regards,
Koichiro Tashiro