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SK-AM62A-LP: Trying to connect an ICS43432 microphone to the SK-AM62A-LP

Part Number: SK-AM62A-LP
Other Parts Discussed in Thread: TLV320AIC3106, TLV320AIC3101, SYSCONFIG

Hi,

I have connected an ICS43432 I2S microphone to MCASP1 (in place of the codec).

In order to get this working, I modified the device tree (k3-am62a7-sk.dts):

diff --git a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts
index 0b101d989..0e8a7c427 100644
--- a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts
+++ b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts
@@ -207,7 +207,7 @@ led-0 {
 			default-state = "off";
 		};
 	};
-
+/*
 	tlv320_mclk: clk-0 {
 		#clock-cells = <0>;
 		compatible = "fixed-clock";
@@ -242,6 +242,28 @@ sound_master: simple-audio-card,codec {
 			clocks = <&tlv320_mclk>;
 		};
 	};
+*/
+	microphone: card-codec {
+		#sound-dai-cells = <0>;
+		compatible = "invensense,ics43432";
+		status = "okay";
+	};
+
+	mic_audio: sound {
+		compatible = "simple-audio-card";
+		simple-audio-card,format = "i2s";
+		simple-audio-card,name = "ics43432";
+		simple-audio-card,bitclock-master = <&sound_master>;
+		simple-audio-card,frame-master = <&sound_master>;
+		status = "okay";
+
+		simple-audio-card,cpu {
+			sound-dai = <&mcasp1>;
+		};
+		sound_master: simple-audio-card,codec {
+			sound-dai = <&microphone>;
+		};
+	};
 
 	hdmi: connector {
 		compatible = "hdmi-connector";
@@ -594,18 +616,18 @@ exp2: gpio@23 {
 				  "CSI_VLDO_SEL", "SoC_WLAN_SDIO_RST";
 	};
 
-	tlv320aic3106: audio-codec@1b {
-		#sound-dai-cells = <0>;
-		compatible = "ti,tlv320aic3106";
-		reg = <0x1b>;
-		ai3x-micbias-vg = <1>;	/* 2.0V */
-		ai3x-ocmv = <1>;	/* 1.5V */
-
-		/* Regulators */
-		AVDD-supply = <&vcc_3v3_sys>;
-		IOVDD-supply = <&vcc_3v3_sys>;
-		DRVDD-supply = <&vcc_3v3_sys>;
-	};
+//	tlv320aic3106: audio-codec@1b {
+//		#sound-dai-cells = <0>;
+//		compatible = "ti,tlv320aic3106";
+//		reg = <0x1b>;
+//		ai3x-micbias-vg = <1>;	/* 2.0V */
+//		ai3x-ocmv = <1>;	/* 1.5V */
+//
+//		/* Regulators */
+//		AVDD-supply = <&vcc_3v3_sys>;
+//		IOVDD-supply = <&vcc_3v3_sys>;
+//		DRVDD-supply = <&vcc_3v3_sys>;
+//	};
 
 	sii9022: sii9022@3b {
 		#sound-dai-cells = <0>;

I comment out the codec parts, and add a simple-sound-card with just the microphone.

The microphone gets recognized by ALSA, so there's that, but when I try to record, I get a timeout getting data.

root@am62axx-evm:~# arecord -Dhw:0 -c2 -r48000 -fS32_LE -twav -d10 -Vstereo test.wav
Recording WAVE 'test.wav' : Signed 32 bit Little Endian, Rate 48000 Hz, Stereo
arecord: pcm_read:2221: read error: Input/output error
[ 1163.429705] ti-udma 485c0100.dma-controller: chan2 teardown timeout!
root@am62axx-evm:~#

Do I have to reconfigure mcasp1 to be able to use I2S? Is there documentation on the device tree options
for the mcasp1 node?

Regards,

Bas Vermeulen

  • I removed the lines with 

    simple-audio-card,bitclock-master = <&sound_master>;
    simple-audio-card,frame-master = <&sound_master>;

    and this gets me further. I now get 

    root@am62axx-evm:/proc/asound# arecord -Dhw:0 -c2 -r 48000 -fS24_LE -twav -d10 -Vstereo ~/test.wav
    Recording WAVE '/home/root/test.wav' : [ 1730.850234] davinci-mcasp 2b10000.audio-controller: Too fast reference clock (
    96000000)
    Signed 24 bit Little Endian, Rate 48000 Hz, Stereo
    Warning: rate is not accurate (requested = 48000Hz, got = 16000Hz)
             please, try the plug plugin
    ^CAborted by signal Interrupt...
    arecord: pcm_read:2221: read error: Input/output error
    [ 1743.781280] ti-udma 485c0100.dma-controller: chan2 teardown timeout!

    According to the driver, the frequency should be between 7190 and 52800 Hz, so I don't understand yet why it's not giving me the 48 kHz I am asking for.

    Is there a procedure to change the reference clock for mcasp1?

    Bas Vermeulen

  • Bas,

    What is the clock you are providing to McASP when you connect this I2S Microphone?

    Also you can refer the k3-am62a7-sk.dts file for Device Tree configuration for McASP.

    Also can you try with 16KHz sampling rate as the received sampling rate is 16KHz instead of 48000.

    Best Regards,

    Suren

  • Hi Suren,

    When using the 16 kHz sampling rate I get the same error. arecord doesn't get above 16 kHz sampling rate when trying to set up the alsa device.
    I've tried 16 kHz sampling rate as well, and that stops arecord from complaining that it got a different rate than requested.
    The reference clock is too fast error stays though. 

    The McASP reference clock is set to 96 MHz, and the driver will complain that it can't divide that down to the clock that's needed.
    I think I need to modify the clock tree to get that McASP reference clock down further (I would need to be able to support 8 kHz up to 48 kHz),
    I'm just not sure where (or how exactly) to do that.

    Regards,

    Bas Vermeulen

  • Bas,

    Have you tried to use the Clock Tree tool to see the configurations required to have proper clocks generated.

    dev.ti.com/.../

    Best Regards,

    Suren

  • Hi Suren,

    Once I modify the clock tree, is there a manual on how to integrate the changes into the build?

    Regards,

    Bas Vermeulen

  • Hi Bas,

    Currently we don't have a manual on how to integrate the changes.

    If you know what the clocks should be you can look at the devicetree bindings for clocks available under Documentation in the kernel.

    https://github.com/devicetree-org/dt-schema/blob/main/dtschema/schemas/clock/clock.yaml

    In our case the TLV320AIC3106 is the master driving the clocks, we have added this:

    https://git.ti.com/cgit/ti-linux-kernel/ti-linux-kernel/tree/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts?h=ti-linux-6.1.y#n211

    If you know what the MCLK is, just add 

    compatible = "fixed-clock";
    clock-frequency = <12288000>; //Replace 12288000 with the value you have figured out using CTT.

    See if this helps.
    Best Regards,
    Suren
  • Hi Suren,

    In our case, the McASP is the clock master, and the microphone is a clock slave. I need to configure the base clock for the mcasp1, which is done by the clock tree tool. If I read the device tree bindings correctly, the TI-SCI is the device that's responsible for the clock frequencies for those.

    I am aware of the clock tree tool, I just need to know where to drop the output of that so that the TI-SCI picks it up (or where to look to be able to make those changes)

    Theoritically, the 96 MHz clock should allow me to use 16 KHz sampling rate (16 kHz * 2 tdm slots * 32 bits per slot can be managed by the 128 divider in the mcasp). sound/soc/ti/davinci-mcasp.c seems to not take into account the physical width of the S24_LE format though, means I can't use 16 kHz (96 MHz / (16 kHz * 24 * 2) = ~130, which is too high). If the driver were to take the physical width instead of params_width in davinci_mcasp_calc_clk_div, it would work. 

    Regards,

    Bas

  • Hi Bas,

    In order to make McASP master, you would need to make the modifications like below in the DTS file:

    codec_audio: sound {
    compatible = "simple-audio-card";
    simple-audio-card,name = "AM62x-SKEVM-MASTER";
    simple-audio-card,widgets =
    "Headphone", "Headphone Jack",
    "Microphone", "Microphone Jack";
    simple-audio-card,routing =
    "Headphone Jack", "HPLOUT",
    "Headphone Jack", "HPROUT",
    "MIC3L", "Microphone Jack",
    "MIC3R", "Microphone Jack",
    "Microphone Jack", "Mic Bias";
    simple-audio-card,format = "i2s";
    simple-audio-card,bitclock-master = <&sound_master>;
    simple-audio-card,frame-master = <&sound_master>;
    simple-audio-card,mclk-fs = <512>;

    sound_master: simple-audio-card,cpu {
    sound-dai = <&mcasp1>;
    system-clock-direction-out;
    };

    simple-audio-card,codec {
    sound-dai = <&tlv320aic3101>;
    clocks = <&audio_refclk1>;
    };
    };
    };

    Let me know if this helps.

    Best Regards,

    Suren

  • Hi Suren,

    I added the following device tree overlay (modified from k3-am62x-sk-hdmi-audio.dtso:

     * Audio recording via ICS43432 for AM625-SK and AM62-LP SK.
     *
     * Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/
     */
    
    /dts-v1/;
    /plugin/;
    
    &{/} {
            ics43432: card-codec {
                    #sound-dai-cells = <0>;
                    compatible = "invensense,ics43432";
                    status = "okay";
            };
    
            ics43432_audio: sound-ics43432 {
                    compatible = "simple-audio-card";
                    simple-audio-card,name = "AM62x-ICS43432";
                    simple-audio-card,format = "i2s";
                    simple-audio-card,bitclock-master = <&mic_dailink_master>;
                    simple-audio-card,frame-master = <&mic_dailink_master>;
                    mic_dailink_master: simple-audio-card,cpu {
                            sound-dai = <&mcasp1>;
                            system-clock-direction-out;
                    };
                    simple-audio-card,codec {
                            sound-dai = <&ics43432>;
                    };
            };
    };
    
    &mcasp1 {
            auxclk-fs-ratio = <2178>;
    };
    
    &codec_audio {
            status = "disabled";
    };
    
    &tlv320aic3106 {
            status = "disabled";
    };
    
    &tlv320_mclk {
            status = "disabled";
    };

    With that applied, I am able to get audio from the microphone, but get the following
    error from davinci-mcasp:

    am62axx-evm:/opt/edgeai-gst-apps# arecord -D hw:0 -c 2 -r 48000 -f S32_LE test
    Recording WAVE 'test.wav' : [  526.307502] davinci-mcasp 2b10000.audio-controller: Sample-rate is off by 8064 PPM
    Signed 32 bit Little Endian, Rate 48000 Hz, Stereo
    ^CAborted by signal Interrupt...
    [  531.107143] ti-udma 485c0100.dma-controller: chan2 teardown timeout!
    root@am62axx-evm:/opt/edgeai-gst-apps#

    Any idea how to modify the sampling rate? I've tried modifying the auxclk-fs-ratio, but that doesn't change anything in that regard.

    48000/32000/16000/8000 Hz are all off by 8064 PPM, 44100 is off by 400 PPM.

    Regards,

    Bas Vermeulen

  • Hi Bas,

    On my AM62A board, although McASP is slave here are the commands I run in order to have recording working for a duration of 20sec :

    root@am62axx-evm:/home# ./alsa-mixer-settings.sh
    Simple mixer control 'Left PGA Mixer Mic3L',0
    Capabilities: pswitch pswitch-joined
    Playback channels: Mono
    Mono: Playback [on]
    Simple mixer control 'Right PGA Mixer Mic3L',0
    Capabilities: pswitch pswitch-joined
    Playback channels: Mono
    Mono: Playback [on]
    Simple mixer control 'Left PGA Mixer Mic3R',0
    Capabilities: pswitch pswitch-joined
    Playback channels: Mono
    Mono: Playback [on]
    Simple mixer control 'Right PGA Mixer Mic3R',0
    Capabilities: pswitch pswitch-joined
    Playback channels: Mono
    Mono: Playback [on]
    Simple mixer control 'PCM',0
    Capabilities: pvolume
    Playback channels: Front Left - Front Right
    Limits: Playback 0 - 127
    Mono:
    Front Left: Playback 127 [100%] [0.00dB]
    Front Right: Playback 127 [100%] [0.00dB]
    root@am62axx-evm:/home#
    root@am62axx-evm:/home# arecord -D hw:0,0 -c 2 -r 48000 -d 20 --period-size=64 -f S32_LE test-48
    Recording WAVE 'test-48' : Signed 32 bit Little Endian, Rate 48000 Hz, Stereo
    [ 1296.673137] ti-udma 485c0100.dma-controller: chan2 teardown timeout!
    root@am62axx-evm:/home# aplay -D hw:0,0 test-48
    Playing WAVE 'test-48' : Signed 32 bit Little Endian, Rate 48000 Hz, Stereo
    [ 1333.153002] ti-udma 485c0100.dma-controller: chan1 teardown timeout!
    root@am62axx-evm:/home# arecord -D hw:0,0 -c 2 -r 16000 -d 20 --period-size=64 -f S32_LE test-16
    Recording WAVE 'test-16' : Signed 32 bit Little Endian, Rate 16000 Hz, Stereo
    [ 1378.176848] ti-udma 485c0100.dma-controller: chan2 teardown timeout!
    root@am62axx-evm:/home# aplay -D hw:0,0 test-16
    Playing WAVE 'test-16' : Signed 32 bit Little Endian, Rate 16000 Hz, Stereo
    [ 1420.032663] ti-udma 485c0100.dma-controller: chan1 teardown timeout!

    Let me know if this helps.

    Best Regards,

    Suren

  • Hi Suren,

    I think I've understood the problem. The I2S microphone needs a 3.072 MHz bit clock, and a 96 kHz frame clock.

    Looking at the schematic, there's a 12.288 MHz crystal connected to AUDIO_EXT_REFCLK1, which would work for this.

    How do I set up the clocks so that McASP1 is using AUDIO_EXT_REFCLK1 for it's system clock?

    I believe I need to set CTRL_MMR0 bits 0-1 and 8-9 to 11b, I just don't know where that's done, or if that's possible to do with a device tree change.

    Regards,

    Bas Vermeulen

  • And I can get audio from the microphone as well. The sampling rate is off (8064 PPM), but I can get audio from it.

    If I can use the AUDIO_EXT_REFCLK1 as input to McASP1, the sampling rate should be perfect.

  • I've found some more specific information on the TISCI manual.

    I would like to use DEV_BOARD0_AUDIO_EXT_REFCLK1_OUT (157:19)  (with a 12.288 MHz crystal) as an input to DEV_MCASP1_MCASP_AHCLKR_PIN (191:9) and DEV_MCASP1_MCASP_AHCLKX_PIN (191:15). I need to use DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT (191:13) and DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT (191:19) as the respective clock parents.

    I can't find how to tell mcasp1 that I would like it to use that configuration, nor how to tell the TISCI that DEV_BOARD0_AUDIO_EXT_REFCLK1_OUT is using a 12.288 MHz crystal to generate it's clock signal.

    When I just change the device tree to use clocks = <&k3_clks 191 9> the clock is assigned, but the 191:9 clock has a rate of 0.

  • Hi ,

    I have the device tree modified to get the clocks set up correctly.

    I use the following device tree overlay to set up the clocks for McASP1:

    // SPDX-License-Identifier: GPL-2.0
    /**
     * Audio recording via ICS43432 for AM625-SK and AM62-LP SK.
     *
     * Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/
     */
    
    /dts-v1/;
    /plugin/;
    
    &{/} {
    	audio_ext_refclk1: clock {
    		compatible = "ti,am62-audio-refclk";
    		#clock-cells = <0>;
    		clocks = <&k3_clks 157 19>;
    		assigned-clocks = <&k3_clks 157 19>;
    		assigned-clock-rates = <12288000>;
    	};
    	
    	ics43432: card-codec {
    		#sound-dai-cells = <0>;
    		compatible = "invensense,ics43432";
    		status = "okay";
    	};
    
    	ics43432_audio: sound-ics43432 {
    		compatible = "simple-audio-card";
    		simple-audio-card,name = "AM62x-ICS43432";
    		simple-audio-card,format = "i2s";
    		simple-audio-card,bitclock-master = <&mic_dailink_master>;
    		simple-audio-card,frame-master = <&mic_dailink_master>;
    		mic_dailink_master: simple-audio-card,cpu {
    			sound-dai = <&mcasp1>;
    			system-clock-direction-out;
    		};
    		simple-audio-card,codec {
    			sound-dai = <&ics43432>;
    		};
    	};
    };
    
    &mcasp1 {
    	clocks = <&k3_clks 191 9>, <&k3_clks 191 15>;
    	assigned-clocks = <&k3_clks 191 9>, <&k3_clks 191 15>;
    	assigned-clock-parents = <&k3_clks 191 13>, <&k3_clks 191 19>;
    };
    
    &codec_audio {
    	status = "disabled";
    };
    
    &tlv320aic3106 {
    	status = "disabled";
    };
    
    &tlv320_mclk {
    	status = "disabled";
    };
    

    This defines an audio_ext_refclk1 that configures clock 157:19 (DEV_BOARD0_AUDIO_EXT_REFCLK1_OUT) as a 12.288 MHz clock (The schematic shows a 12.288 MHz clocking being connected to AUDIO_EXT_REFCLK1).

    The clock 191:9 (DEV_MCASP1_MCASP_AHCLKR_PIN) is connected to 191:13 (DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT), and clock 191:15 (DEV_MCASP1_MCASP_AHCLKX_PIN) is connected to 191:19 (DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT). Using clocks 191:15 and 191:19 as parents should connect the clocks to DEV_BOARD0_AUDIO_EXT_REFCLK1.

    This logically connects everything correctly. For some reason, my bitclock is derived from clock 157:10 (DEV_BOARD0_AUDIO_EXT_REFCLK1_IN).
    When I measure my bitclock, I get 16.7 MHz instead of the 2.048 MHz I would expect with my 32 kHz sampling rate. The ratio between the real bitclock and the expected bitclock corresponds to the input clock being 100 MHz instead of 12.288 MHz.

    Any idea what is going wrong?

    Regards,

    Bas Vermeulen

  • Bas

    Check the divider and mux settings in the clock path of the McASP be used and confirm they are as you expect. Refer to figure 12-13 in the TRM. 

    The ratio between the source clock and the bit/Word clocks will always be an an integer divider. 

    --Paul 

  • Hi Paul,

    Is there a way to read the MCASP_ACLKRCTL register from userspace? I've tried using devmem2 (devmem2 0x2b20070) but that gives me a bus error.

    I can try modifying the driver to print that, but if there's a way to do it with the tools on the evm board that would be great.

    Bas Vermeulen

  • Which MCASP are you trying to read and what register address? A bus error is typical when a peripheral is not enabled,

    --Paul 

  • I'm trying to read MCASP_ACLKRCTL (0x70h) on McASP1. According to the TRM this is 02B1 0070h.

    When I read try to read the register while not recording, I get the bus error, when I am recording I get the following:

    root@am62axx-evm:~/4kcam/src# devmem2 0x2b10070
    /dev/mem opened.
    Memory mapped at address 0xffff8f968000.
    Read at address 0x02B10070 (0xffff8f968070): 0x001800A0

    I can't find the register definition in the TRM, but from the figure you gave, the divider seems to be 0.

    What registers should I evaluate for this?

    Bas

  • Bas,

    On your setup can you share the output of the command and share:

    k3conf dump clock 157

    Best Regards,

    Suren

  • Hi Suren,

    root@am62axx-evm:/opt/edgeai-gst-apps# k3conf dump clock 157
    |------------------------------------------------------------------------------|
    | VERSION INFO                                                                 |
    |------------------------------------------------------------------------------|
    | K3CONF | (version 0.3-nogit built Fri Oct 06 12:20:16 UTC 2023)              |
    | SoC    | AM62Ax SR1.0                                                        |
    | SYSFW  | ABI: 3.1 (firmware version 0x0009 '9.1.8--v09.01.08 (Kool Koala))') |
    |------------------------------------------------------------------------------|
    
    |-------------------------------------------------------------------------------------------------------------------------------------------|
    | Device ID | Clock ID | Clock Name                                                                 | Status
      | Clock Frequency |
    |-------------------------------------------------------------------------------------------------------------------------------------------|
    |   157     |     0    | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN                                            | CLK_STATE_READY     | 100000000       |
    |   157     |     1    | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT      | CLK_STATE_NOT_READY | 0               |
    |   157     |     2    | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT      | CLK_STATE_NOT_READY | 0               |
    |   157     |     3    | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT      | CLK_STATE_NOT_READY | 0               |
    |   157     |     4    | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT      | CLK_STATE_NOT_READY | 0               |
    |   157     |     5    | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT      | CLK_STATE_NOT_READY | 0               |
    |   157     |     6    | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT      | CLK_STATE_NOT_READY | 0               |
    |   157     |     7    | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_POSTDIV1_16FFT_MAIN_1_HSDIVOUT6_CLK | CLK_STATE_READY     | 96000000        |
    |   157     |     8    | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT8_CLK  | CLK_STATE_READY     | 100000000       |
    |   157     |     9    | DEV_BOARD0_AUDIO_EXT_REFCLK0_OUT                                           | CLK_STATE_READY     | 0               |
    |   157     |    10    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN                                            | CLK_STATE_READY     | 100000000       |
    |   157     |    11    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT      | CLK_STATE_NOT_READY | 0               |
    |   157     |    12    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT      | CLK_STATE_NOT_READY | 0               |
    |   157     |    13    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT      | CLK_STATE_NOT_READY | 0               |
    |   157     |    14    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT      | CLK_STATE_NOT_READY | 0               |
    |   157     |    15    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT      | CLK_STATE_NOT_READY | 0               |
    |   157     |    16    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT      | CLK_STATE_NOT_READY | 0               |
    |   157     |    17    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_POSTDIV1_16FFT_MAIN_1_HSDIVOUT6_CLK | CLK_STATE_READY     | 96000000        |
    |   157     |    18    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT8_CLK  | CLK_STATE_READY     | 100000000       |
    |   157     |    19    | DEV_BOARD0_AUDIO_EXT_REFCLK1_OUT                                           | CLK_STATE_READY     | 0               |
    |   157     |    20    | DEV_BOARD0_CLKOUT0_IN                                                      | CLK_STATE_READY     | 50000000        |
    |   157     |    21    | DEV_BOARD0_CLKOUT0_IN_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK5            | CLK_STATE_READY     | 50000000        |
    |   157     |    22    | DEV_BOARD0_CLKOUT0_IN_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK10           | CLK_STATE_READY     | 25000000        |
    |   157     |    23    | DEV_BOARD0_CP_GEMAC_CPTS0_RFT_CLK_OUT                                      | CLK_STATE_READY     | 0               |
    |   157     |    24    | DEV_BOARD0_DDR0_CK0_IN                                                     | CLK_STATE_READY     | 250000000       |
    |   157     |    25    | DEV_BOARD0_DDR0_CK0_N_IN                                                   | CLK_STATE_READY     | 0               |
    |   157     |    27    | DEV_BOARD0_DDR0_CK0_OUT                                                    | CLK_STATE_READY     | 0               |
    |   157     |    33    | DEV_BOARD0_EXT_REFCLK1_OUT                                                 | CLK_STATE_READY     | 0               |
    |   157     |    34    | DEV_BOARD0_GPMC0_CLKLB_IN                                                  | CLK_STATE_READY     | 0               |
    |   157     |    35    | DEV_BOARD0_GPMC0_CLKLB_OUT                                                 | CLK_STATE_READY     | 0               |
    |   157     |    36    | DEV_BOARD0_GPMC0_CLK_IN                                                    | CLK_STATE_READY     | 0               |
    |   157     |    37    | DEV_BOARD0_GPMC0_FCLK_MUX_IN                                               | CLK_STATE_READY     | 133333333       |
    |   157     |    38    | DEV_BOARD0_GPMC0_FCLK_MUX_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT3_CLK      | CLK_STATE_READY     | 133333333       |
    |   157     |    39    | DEV_BOARD0_GPMC0_FCLK_MUX_IN_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT7_CLK     | CLK_STATE_READY     | 100000000       |
    |   157     |    40    | DEV_BOARD0_I2C0_SCL_IN                                                     | CLK_STATE_READY     | 0               |
    |   157     |    41    | DEV_BOARD0_I2C0_SCL_OUT                                                    | CLK_STATE_READY     | 0               |
    |   157     |    42    | DEV_BOARD0_I2C1_SCL_IN                                                     | CLK_STATE_READY     | 0               |
    |   157     |    43    | DEV_BOARD0_I2C1_SCL_OUT                                                    | CLK_STATE_READY     | 0               |
    |   157     |    44    | DEV_BOARD0_I2C2_SCL_IN                                                     | CLK_STATE_READY     | 0               |
    |   157     |    45    | DEV_BOARD0_I2C2_SCL_OUT                                                    | CLK_STATE_READY     | 0               |
    |   157     |    46    | DEV_BOARD0_I2C3_SCL_IN                                                     | CLK_STATE_READY     | 0               |
    |   157     |    47    | DEV_BOARD0_I2C3_SCL_OUT                                                    | CLK_STATE_READY     | 0               |
    |   157     |    49    | DEV_BOARD0_MCASP0_ACLKR_IN                                                 | CLK_STATE_READY     | 0               |
    |   157     |    50    | DEV_BOARD0_MCASP0_ACLKR_OUT                                                | CLK_STATE_READY     | 0               |
    |   157     |    51    | DEV_BOARD0_MCASP0_ACLKX_IN                                                 | CLK_STATE_READY     | 0               |
    |   157     |    52    | DEV_BOARD0_MCASP0_ACLKX_OUT                                                | CLK_STATE_READY     | 0               |
    |   157     |    53    | DEV_BOARD0_MCASP0_AFSR_IN                                                  | CLK_STATE_READY     | 0               |
    |   157     |    54    | DEV_BOARD0_MCASP0_AFSX_IN                                                  | CLK_STATE_READY     | 0               |
    |   157     |    55    | DEV_BOARD0_MCASP1_ACLKR_IN                                                 | CLK_STATE_READY     | 0               |
    |   157     |    56    | DEV_BOARD0_MCASP1_ACLKR_OUT                                                | CLK_STATE_READY     | 0               |
    |   157     |    57    | DEV_BOARD0_MCASP1_ACLKX_IN                                                 | CLK_STATE_READY     | 0               |
    |   157     |    58    | DEV_BOARD0_MCASP1_ACLKX_OUT                                                | CLK_STATE_READY     | 0               |
    |   157     |    59    | DEV_BOARD0_MCASP1_AFSR_IN                                                  | CLK_STATE_READY     | 0               |
    |   157     |    60    | DEV_BOARD0_MCASP1_AFSX_IN                                                  | CLK_STATE_READY     | 0               |
    |   157     |    61    | DEV_BOARD0_MCASP2_ACLKR_IN                                                 | CLK_STATE_READY     | 0               |
    |   157     |    62    | DEV_BOARD0_MCASP2_ACLKR_OUT                                                | CLK_STATE_READY     | 0               |
    |   157     |    63    | DEV_BOARD0_MCASP2_ACLKX_IN                                                 | CLK_STATE_READY     | 0               |
    |   157     |    64    | DEV_BOARD0_MCASP2_ACLKX_OUT                                                | CLK_STATE_READY     | 0               |
    |   157     |    65    | DEV_BOARD0_MCASP2_AFSR_IN                                                  | CLK_STATE_READY     | 0               |
    |   157     |    66    | DEV_BOARD0_MCASP2_AFSX_IN                                                  | CLK_STATE_READY     | 0               |
    |   157     |    67    | DEV_BOARD0_MCU_EXT_REFCLK0_OUT                                             | CLK_STATE_READY     | 0               |
    |   157     |    69    | DEV_BOARD0_MCU_I2C0_SCL_OUT                                                | CLK_STATE_READY     | 0               |
    |   157     |    70    | DEV_BOARD0_MCU_OBSCLK0_IN                                                  | CLK_STATE_READY     | 12500000        |
    |   157     |    71    | DEV_BOARD0_MCU_OBSCLK0_IN_PARENT_MCU_OBSCLK_DIV_OUT0                       | CLK_STATE_READY     | 12500000        |
    |   157     |    72    | DEV_BOARD0_MCU_OBSCLK0_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT                   | CLK_STATE_READY     | 25000000        |
    |   157     |    73    | DEV_BOARD0_MCU_SPI0_CLK_IN                                                 | CLK_STATE_READY     | 0               |
    |   157     |    74    | DEV_BOARD0_MCU_SPI0_CLK_OUT                                                | CLK_STATE_READY     | 0               |
    |   157     |    75    | DEV_BOARD0_MCU_SPI1_CLK_IN                                                 | CLK_STATE_READY     | 0               |
    |   157     |    76    | DEV_BOARD0_MCU_SPI1_CLK_OUT                                                | CLK_STATE_READY     | 0               |
    |   157     |    77    | DEV_BOARD0_MCU_SYSCLKOUT0_IN                                               | CLK_STATE_READY     | 100000000       |
    |   157     |    78    | DEV_BOARD0_MCU_TIMER_IO0_IN                                                | CLK_STATE_READY     | 0               |
    |   157     |    79    | DEV_BOARD0_MCU_TIMER_IO1_IN                                                | CLK_STATE_READY     | 0               |
    |   157     |    80    | DEV_BOARD0_MCU_TIMER_IO2_IN                                                | CLK_STATE_READY     | 0               |
    |   157     |    81    | DEV_BOARD0_MCU_TIMER_IO3_IN                                                | CLK_STATE_READY     | 0               |
    |   157     |    82    | DEV_BOARD0_MDIO0_MDC_IN                                                    | CLK_STATE_READY     | 0               |
    |   157     |    83    | DEV_BOARD0_MMC0_CLKLB_IN                                                   | CLK_STATE_READY     | 0               |
    |   157     |    84    | DEV_BOARD0_MMC0_CLKLB_OUT                                                  | CLK_STATE_READY     | 0               |
    |   157     |    85    | DEV_BOARD0_MMC0_CLK_IN                                                     | CLK_STATE_READY     | 0               |
    |   157     |    86    | DEV_BOARD0_MMC0_CLK_OUT                                                    | CLK_STATE_READY     | 0               |
    |   157     |    87    | DEV_BOARD0_MMC1_CLKLB_IN                                                   | CLK_STATE_READY     | 0               |
    |   157     |    88    | DEV_BOARD0_MMC1_CLKLB_OUT                                                  | CLK_STATE_READY     | 0               |
    |   157     |    89    | DEV_BOARD0_MMC1_CLK_IN                                                     | CLK_STATE_READY     | 0               |
    |   157     |    90    | DEV_BOARD0_MMC1_CLK_OUT                                                    | CLK_STATE_READY     | 0               |
    |   157     |    91    | DEV_BOARD0_MMC2_CLKLB_IN                                                   | CLK_STATE_READY     | 0               |
    |   157     |    92    | DEV_BOARD0_MMC2_CLKLB_OUT                                                  | CLK_STATE_READY     | 0               |
    |   157     |    93    | DEV_BOARD0_MMC2_CLK_IN                                                     | CLK_STATE_READY     | 0               |
    |   157     |    94    | DEV_BOARD0_MMC2_CLK_OUT                                                    | CLK_STATE_READY     | 0               |
    |   157     |    95    | DEV_BOARD0_OBSCLK0_IN                                                      | CLK_STATE_READY     | 500000000       |
    |   157     |    96    | DEV_BOARD0_OBSCLK0_IN_PARENT_MAIN_OBSCLK_DIV_OUT0                          | CLK_STATE_READY     | 500000000       |
    |   157     |    97    | DEV_BOARD0_OBSCLK0_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT                       | CLK_STATE_READY     | 25000000        |
    |   157     |   128    | DEV_BOARD0_OBSCLK1_IN                                                      | CLK_STATE_READY     | 500000000       |
    |   157     |   129    | DEV_BOARD0_OSPI0_DQS_OUT                                                   | CLK_STATE_READY     | 0               |
    |   157     |   130    | DEV_BOARD0_OSPI0_LBCLKO_IN                                                 | CLK_STATE_READY     | 0               |
    |   157     |   131    | DEV_BOARD0_OSPI0_LBCLKO_OUT                                                | CLK_STATE_READY     | 0               |
    |   157     |   132    | DEV_BOARD0_RGMII1_RXC_OUT                                                  | CLK_STATE_READY     | 0               |
    |   157     |   133    | DEV_BOARD0_RGMII1_TXC_IN                                                   | CLK_STATE_READY     | 0               |
    |   157     |   134    | DEV_BOARD0_RGMII1_TXC_OUT                                                  | CLK_STATE_READY     | 0               |
    |   157     |   135    | DEV_BOARD0_RGMII2_RXC_OUT                                                  | CLK_STATE_READY     | 0               |
    |   157     |   136    | DEV_BOARD0_RGMII2_TXC_IN                                                   | CLK_STATE_READY     | 0               |
    |   157     |   137    | DEV_BOARD0_RGMII2_TXC_OUT                                                  | CLK_STATE_READY     | 0               |
    |   157     |   138    | DEV_BOARD0_RMII1_REF_CLK_OUT                                               | CLK_STATE_READY     | 0               |
    |   157     |   139    | DEV_BOARD0_RMII2_REF_CLK_OUT                                               | CLK_STATE_READY     | 0               |
    |   157     |   140    | DEV_BOARD0_SPI0_CLK_IN                                                     | CLK_STATE_READY     | 0               |
    |   157     |   141    | DEV_BOARD0_SPI0_CLK_OUT                                                    | CLK_STATE_READY     | 0               |
    |   157     |   142    | DEV_BOARD0_SPI1_CLK_IN                                                     | CLK_STATE_READY     | 0               |
    |   157     |   143    | DEV_BOARD0_SPI1_CLK_OUT                                                    | CLK_STATE_READY     | 0               |
    |   157     |   144    | DEV_BOARD0_SPI2_CLK_IN                                                     | CLK_STATE_READY     | 0               |
    |   157     |   145    | DEV_BOARD0_SPI2_CLK_OUT                                                    | CLK_STATE_READY     | 0               |
    |   157     |   146    | DEV_BOARD0_SYSCLKOUT0_IN                                                   | CLK_STATE_READY     | 125000000       |
    |   157     |   147    | DEV_BOARD0_TCK_OUT                                                         | CLK_STATE_READY     | 0               |
    |   157     |   148    | DEV_BOARD0_TIMER_IO0_IN                                                    | CLK_STATE_READY     | 0               |
    |   157     |   149    | DEV_BOARD0_TIMER_IO1_IN                                                    | CLK_STATE_READY     | 0               |
    |   157     |   150    | DEV_BOARD0_TIMER_IO2_IN                                                    | CLK_STATE_READY     | 0               |
    |   157     |   151    | DEV_BOARD0_TIMER_IO3_IN                                                    | CLK_STATE_READY     | 0               |
    |   157     |   152    | DEV_BOARD0_TIMER_IO4_IN                                                    | CLK_STATE_READY     | 0               |
    |   157     |   153    | DEV_BOARD0_TIMER_IO5_IN                                                    | CLK_STATE_READY     | 0               |
    |   157     |   154    | DEV_BOARD0_TIMER_IO6_IN                                                    | CLK_STATE_READY     | 0               |
    |   157     |   155    | DEV_BOARD0_TIMER_IO7_IN                                                    | CLK_STATE_READY     | 0               |
    |   157     |   156    | DEV_BOARD0_TRC_CLK_IN                                                      | CLK_STATE_READY     | 0               |
    |   157     |   157    | DEV_BOARD0_VOUT0_EXTPCLKIN_OUT                                             | CLK_STATE_READY     | 0               |
    |   157     |   158    | DEV_BOARD0_VOUT0_PCLK_IN                                                   | CLK_STATE_READY     | 0               |
    |   157     |   159    | DEV_BOARD0_WKUP_CLKOUT0_IN                                                 | CLK_STATE_NOT_READY | 0               |
    |   157     |   160    | DEV_BOARD0_WKUP_CLKOUT0_IN_PARENT_WKUP_CLKOUT_SEL_OUT0                     | CLK_STATE_NOT_READY | 0               |
    |   157     |   161    | DEV_BOARD0_WKUP_CLKOUT0_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT                  | CLK_STATE_READY     | 25000000        |
    |-------------------------------------------------------------------------------------------------------------------------------------------|
    
    root@am62axx-evm:/opt/edgeai-gst-apps#

  • Hi Bas,

    Could you provide the entire register dump for MCASP1 that you are using in your setup?

    Also, k3conf dump for 191 that you are using as parent. 

    Best Regards,

    Suren

  • Hi Suren,

    Using this device tree overlay:

    // SPDX-License-Identifier: GPL-2.0
    /**
     * Audio recording via ICS43432 for AM625-SK and AM62-LP SK.
     *
     * Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/
     */
    
    /dts-v1/;
    /plugin/;
    
    &{/} {
    	audio_ext_refclk1: clock {
    		compatible = "ti,am62-audio-refclk";
    		#clock-cells = <0>;
    		clocks = <&k3_clks 157 19>;
    		assigned-clocks = <&k3_clks 157 19>;
    		assigned-clock-rates = <12288000>;
    	};
    	
    	ics43432: card-codec {
    		#sound-dai-cells = <0>;
    		compatible = "invensense,ics43432";
    		status = "okay";
    	};
    
    	ics43432_audio: sound-ics43432 {
    		compatible = "simple-audio-card";
    		simple-audio-card,name = "AM62x-ICS43432";
    		simple-audio-card,format = "i2s";
    		simple-audio-card,bitclock-master = <&mic_dailink_master>;
    		simple-audio-card,frame-master = <&mic_dailink_master>;
    		mic_dailink_master: simple-audio-card,cpu {
    			sound-dai = <&mcasp1>;
    			system-clock-direction-out;
    		};
    		simple-audio-card,codec {
    			sound-dai = <&ics43432>;
    		};
    	};
    };
    
    &mcasp1 {
    	clocks = <&k3_clks 191 9>, <&k3_clks 191 15>;
    	assigned-clocks = <&k3_clks 191 9>, <&k3_clks 191 15>;
    	assigned-clock-parents = <&k3_clks 191 13>, <&k3_clks 191 19>;
    };
    
    &codec_audio {
    	status = "disabled";
    };
    
    &tlv320aic3106 {
    	status = "disabled";
    };
    
    &tlv320_mclk {
    	status = "disabled";
    };

    I get the following outputs:

    k3conf dump clock 157:

    |------------------------------------------------------------------------------|
    | VERSION INFO                                                                 |
    |------------------------------------------------------------------------------|
    | K3CONF | (version 0.3-nogit built Fri Oct 06 12:20:16 UTC 2023)              |
    | SoC    | AM62Ax SR1.0                                                        |
    | SYSFW  | ABI: 3.1 (firmware version 0x0009 '9.1.8--v09.01.08 (Kool Koala))') |
    |------------------------------------------------------------------------------|
    
    |-------------------------------------------------------------------------------------------------------------------------------------------|
    | Device ID | Clock ID | Clock Name                                                                 | Status              | Clock Frequency |
    |-------------------------------------------------------------------------------------------------------------------------------------------|
    |   157     |     0    | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN                                            | CLK_STATE_READY     | 100000000       |
    |   157     |     1    | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT      | CLK_STATE_NOT_READY | 0               |
    |   157     |     2    | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT      | CLK_STATE_READY     | 0               |
    |   157     |     3    | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT      | CLK_STATE_NOT_READY | 0               |
    |   157     |     4    | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT      | CLK_STATE_NOT_READY | 0               |
    |   157     |     5    | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT      | CLK_STATE_READY     | 0               |
    |   157     |     6    | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT      | CLK_STATE_NOT_READY | 0               |
    |   157     |     7    | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_POSTDIV1_16FFT_MAIN_1_HSDIVOUT6_CLK | CLK_STATE_READY     | 96000000        |
    |   157     |     8    | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT8_CLK  | CLK_STATE_READY     | 100000000       |
    |   157     |     9    | DEV_BOARD0_AUDIO_EXT_REFCLK0_OUT                                           | CLK_STATE_READY     | 0               |
    |   157     |    10    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN                                            | CLK_STATE_READY     | 100000000       |
    |   157     |    11    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT      | CLK_STATE_NOT_READY | 0               |
    |   157     |    12    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT      | CLK_STATE_READY     | 0               |
    |   157     |    13    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT      | CLK_STATE_NOT_READY | 0               |
    |   157     |    14    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT      | CLK_STATE_NOT_READY | 0               |
    |   157     |    15    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT      | CLK_STATE_READY     | 0               |
    |   157     |    16    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT      | CLK_STATE_NOT_READY | 0               |
    |   157     |    17    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_POSTDIV1_16FFT_MAIN_1_HSDIVOUT6_CLK | CLK_STATE_READY     | 96000000        |
    |   157     |    18    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT8_CLK  | CLK_STATE_READY     | 100000000       |
    |   157     |    19    | DEV_BOARD0_AUDIO_EXT_REFCLK1_OUT                                           | CLK_STATE_READY     | 12288000        |
    |   157     |    20    | DEV_BOARD0_CLKOUT0_IN                                                      | CLK_STATE_READY     | 50000000        |
    |   157     |    21    | DEV_BOARD0_CLKOUT0_IN_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK5            | CLK_STATE_READY     | 50000000        |
    |   157     |    22    | DEV_BOARD0_CLKOUT0_IN_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK10           | CLK_STATE_READY     | 25000000        |
    |   157     |    23    | DEV_BOARD0_CP_GEMAC_CPTS0_RFT_CLK_OUT                                      | CLK_STATE_READY     | 0               |
    |   157     |    24    | DEV_BOARD0_DDR0_CK0_IN                                                     | CLK_STATE_READY     | 250000000       |
    |   157     |    25    | DEV_BOARD0_DDR0_CK0_N_IN                                                   | CLK_STATE_READY     | 0               |
    |   157     |    27    | DEV_BOARD0_DDR0_CK0_OUT                                                    | CLK_STATE_READY     | 0               |
    |   157     |    33    | DEV_BOARD0_EXT_REFCLK1_OUT                                                 | CLK_STATE_READY     | 0               |
    |   157     |    34    | DEV_BOARD0_GPMC0_CLKLB_IN                                                  | CLK_STATE_READY     | 0               |
    |   157     |    35    | DEV_BOARD0_GPMC0_CLKLB_OUT                                                 | CLK_STATE_READY     | 0               |
    |   157     |    36    | DEV_BOARD0_GPMC0_CLK_IN                                                    | CLK_STATE_READY     | 0               |
    |   157     |    37    | DEV_BOARD0_GPMC0_FCLK_MUX_IN                                               | CLK_STATE_READY     | 133333333       |
    |   157     |    38    | DEV_BOARD0_GPMC0_FCLK_MUX_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT3_CLK      | CLK_STATE_READY     | 133333333       |
    |   157     |    39    | DEV_BOARD0_GPMC0_FCLK_MUX_IN_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT7_CLK     | CLK_STATE_READY     | 100000000       |
    |   157     |    40    | DEV_BOARD0_I2C0_SCL_IN                                                     | CLK_STATE_READY     | 0               |
    |   157     |    41    | DEV_BOARD0_I2C0_SCL_OUT                                                    | CLK_STATE_READY     | 0               |
    |   157     |    42    | DEV_BOARD0_I2C1_SCL_IN                                                     | CLK_STATE_READY     | 0               |
    |   157     |    43    | DEV_BOARD0_I2C1_SCL_OUT                                                    | CLK_STATE_READY     | 0               |
    |   157     |    44    | DEV_BOARD0_I2C2_SCL_IN                                                     | CLK_STATE_READY     | 0               |
    |   157     |    45    | DEV_BOARD0_I2C2_SCL_OUT                                                    | CLK_STATE_READY     | 0               |
    |   157     |    46    | DEV_BOARD0_I2C3_SCL_IN                                                     | CLK_STATE_READY     | 0               |
    |   157     |    47    | DEV_BOARD0_I2C3_SCL_OUT                                                    | CLK_STATE_READY     | 0               |
    |   157     |    49    | DEV_BOARD0_MCASP0_ACLKR_IN                                                 | CLK_STATE_READY     | 0               |
    |   157     |    50    | DEV_BOARD0_MCASP0_ACLKR_OUT                                                | CLK_STATE_READY     | 0               |
    |   157     |    51    | DEV_BOARD0_MCASP0_ACLKX_IN                                                 | CLK_STATE_READY     | 0               |
    |   157     |    52    | DEV_BOARD0_MCASP0_ACLKX_OUT                                                | CLK_STATE_READY     | 0               |
    |   157     |    53    | DEV_BOARD0_MCASP0_AFSR_IN                                                  | CLK_STATE_READY     | 0               |
    |   157     |    54    | DEV_BOARD0_MCASP0_AFSX_IN                                                  | CLK_STATE_READY     | 0               |
    |   157     |    55    | DEV_BOARD0_MCASP1_ACLKR_IN                                                 | CLK_STATE_READY     | 0               |
    |   157     |    56    | DEV_BOARD0_MCASP1_ACLKR_OUT                                                | CLK_STATE_READY     | 0               |
    |   157     |    57    | DEV_BOARD0_MCASP1_ACLKX_IN                                                 | CLK_STATE_READY     | 0               |
    |   157     |    58    | DEV_BOARD0_MCASP1_ACLKX_OUT                                                | CLK_STATE_READY     | 0               |
    |   157     |    59    | DEV_BOARD0_MCASP1_AFSR_IN                                                  | CLK_STATE_READY     | 0               |
    |   157     |    60    | DEV_BOARD0_MCASP1_AFSX_IN                                                  | CLK_STATE_READY     | 0               |
    |   157     |    61    | DEV_BOARD0_MCASP2_ACLKR_IN                                                 | CLK_STATE_READY     | 0               |
    |   157     |    62    | DEV_BOARD0_MCASP2_ACLKR_OUT                                                | CLK_STATE_READY     | 0               |
    |   157     |    63    | DEV_BOARD0_MCASP2_ACLKX_IN                                                 | CLK_STATE_READY     | 0               |
    |   157     |    64    | DEV_BOARD0_MCASP2_ACLKX_OUT                                                | CLK_STATE_READY     | 0               |
    |   157     |    65    | DEV_BOARD0_MCASP2_AFSR_IN                                                  | CLK_STATE_READY     | 0               |
    |   157     |    66    | DEV_BOARD0_MCASP2_AFSX_IN                                                  | CLK_STATE_READY     | 0               |
    |   157     |    67    | DEV_BOARD0_MCU_EXT_REFCLK0_OUT                                             | CLK_STATE_READY     | 0               |
    |   157     |    69    | DEV_BOARD0_MCU_I2C0_SCL_OUT                                                | CLK_STATE_READY     | 0               |
    |   157     |    70    | DEV_BOARD0_MCU_OBSCLK0_IN                                                  | CLK_STATE_READY     | 12500000        |
    |   157     |    71    | DEV_BOARD0_MCU_OBSCLK0_IN_PARENT_MCU_OBSCLK_DIV_OUT0                       | CLK_STATE_READY     | 12500000        |
    |   157     |    72    | DEV_BOARD0_MCU_OBSCLK0_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT                   | CLK_STATE_READY     | 25000000        |
    |   157     |    73    | DEV_BOARD0_MCU_SPI0_CLK_IN                                                 | CLK_STATE_READY     | 0               |
    |   157     |    74    | DEV_BOARD0_MCU_SPI0_CLK_OUT                                                | CLK_STATE_READY     | 0               |
    |   157     |    75    | DEV_BOARD0_MCU_SPI1_CLK_IN                                                 | CLK_STATE_READY     | 0               |
    |   157     |    76    | DEV_BOARD0_MCU_SPI1_CLK_OUT                                                | CLK_STATE_READY     | 0               |
    |   157     |    77    | DEV_BOARD0_MCU_SYSCLKOUT0_IN                                               | CLK_STATE_READY     | 100000000       |
    |   157     |    78    | DEV_BOARD0_MCU_TIMER_IO0_IN                                                | CLK_STATE_READY     | 0               |
    |   157     |    79    | DEV_BOARD0_MCU_TIMER_IO1_IN                                                | CLK_STATE_READY     | 0               |
    |   157     |    80    | DEV_BOARD0_MCU_TIMER_IO2_IN                                                | CLK_STATE_READY     | 0               |
    |   157     |    81    | DEV_BOARD0_MCU_TIMER_IO3_IN                                                | CLK_STATE_READY     | 0               |
    |   157     |    82    | DEV_BOARD0_MDIO0_MDC_IN                                                    | CLK_STATE_READY     | 0               |
    |   157     |    83    | DEV_BOARD0_MMC0_CLKLB_IN                                                   | CLK_STATE_READY     | 0               |
    |   157     |    84    | DEV_BOARD0_MMC0_CLKLB_OUT                                                  | CLK_STATE_READY     | 0               |
    |   157     |    85    | DEV_BOARD0_MMC0_CLK_IN                                                     | CLK_STATE_READY     | 0               |
    |   157     |    86    | DEV_BOARD0_MMC0_CLK_OUT                                                    | CLK_STATE_READY     | 0               |
    |   157     |    87    | DEV_BOARD0_MMC1_CLKLB_IN                                                   | CLK_STATE_READY     | 0               |
    |   157     |    88    | DEV_BOARD0_MMC1_CLKLB_OUT                                                  | CLK_STATE_READY     | 0               |
    |   157     |    89    | DEV_BOARD0_MMC1_CLK_IN                                                     | CLK_STATE_READY     | 0               |
    |   157     |    90    | DEV_BOARD0_MMC1_CLK_OUT                                                    | CLK_STATE_READY     | 0               |
    |   157     |    91    | DEV_BOARD0_MMC2_CLKLB_IN                                                   | CLK_STATE_READY     | 0               |
    |   157     |    92    | DEV_BOARD0_MMC2_CLKLB_OUT                                                  | CLK_STATE_READY     | 0               |
    |   157     |    93    | DEV_BOARD0_MMC2_CLK_IN                                                     | CLK_STATE_READY     | 0               |
    |   157     |    94    | DEV_BOARD0_MMC2_CLK_OUT                                                    | CLK_STATE_READY     | 0               |
    |   157     |    95    | DEV_BOARD0_OBSCLK0_IN                                                      | CLK_STATE_READY     | 500000000       |
    |   157     |    96    | DEV_BOARD0_OBSCLK0_IN_PARENT_MAIN_OBSCLK_DIV_OUT0                          | CLK_STATE_READY     | 500000000       |
    |   157     |    97    | DEV_BOARD0_OBSCLK0_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT                       | CLK_STATE_READY     | 25000000        |
    |   157     |   128    | DEV_BOARD0_OBSCLK1_IN                                                      | CLK_STATE_READY     | 500000000       |
    |   157     |   129    | DEV_BOARD0_OSPI0_DQS_OUT                                                   | CLK_STATE_READY     | 0               |
    |   157     |   130    | DEV_BOARD0_OSPI0_LBCLKO_IN                                                 | CLK_STATE_READY     | 0               |
    |   157     |   131    | DEV_BOARD0_OSPI0_LBCLKO_OUT                                                | CLK_STATE_READY     | 0               |
    |   157     |   132    | DEV_BOARD0_RGMII1_RXC_OUT                                                  | CLK_STATE_READY     | 0               |
    |   157     |   133    | DEV_BOARD0_RGMII1_TXC_IN                                                   | CLK_STATE_READY     | 0               |
    |   157     |   134    | DEV_BOARD0_RGMII1_TXC_OUT                                                  | CLK_STATE_READY     | 0               |
    |   157     |   135    | DEV_BOARD0_RGMII2_RXC_OUT                                                  | CLK_STATE_READY     | 0               |
    |   157     |   136    | DEV_BOARD0_RGMII2_TXC_IN                                                   | CLK_STATE_READY     | 0               |
    |   157     |   137    | DEV_BOARD0_RGMII2_TXC_OUT                                                  | CLK_STATE_READY     | 0               |
    |   157     |   138    | DEV_BOARD0_RMII1_REF_CLK_OUT                                               | CLK_STATE_READY     | 0               |
    |   157     |   139    | DEV_BOARD0_RMII2_REF_CLK_OUT                                               | CLK_STATE_READY     | 0               |
    |   157     |   140    | DEV_BOARD0_SPI0_CLK_IN                                                     | CLK_STATE_READY     | 0               |
    |   157     |   141    | DEV_BOARD0_SPI0_CLK_OUT                                                    | CLK_STATE_READY     | 0               |
    |   157     |   142    | DEV_BOARD0_SPI1_CLK_IN                                                     | CLK_STATE_READY     | 0               |
    |   157     |   143    | DEV_BOARD0_SPI1_CLK_OUT                                                    | CLK_STATE_READY     | 0               |
    |   157     |   144    | DEV_BOARD0_SPI2_CLK_IN                                                     | CLK_STATE_READY     | 0               |
    |   157     |   145    | DEV_BOARD0_SPI2_CLK_OUT                                                    | CLK_STATE_READY     | 0               |
    |   157     |   146    | DEV_BOARD0_SYSCLKOUT0_IN                                                   | CLK_STATE_READY     | 125000000       |
    |   157     |   147    | DEV_BOARD0_TCK_OUT                                                         | CLK_STATE_READY     | 0               |
    |   157     |   148    | DEV_BOARD0_TIMER_IO0_IN                                                    | CLK_STATE_READY     | 0               |
    |   157     |   149    | DEV_BOARD0_TIMER_IO1_IN                                                    | CLK_STATE_READY     | 0               |
    |   157     |   150    | DEV_BOARD0_TIMER_IO2_IN                                                    | CLK_STATE_READY     | 0               |
    |   157     |   151    | DEV_BOARD0_TIMER_IO3_IN                                                    | CLK_STATE_READY     | 0               |
    |   157     |   152    | DEV_BOARD0_TIMER_IO4_IN                                                    | CLK_STATE_READY     | 0               |
    |   157     |   153    | DEV_BOARD0_TIMER_IO5_IN                                                    | CLK_STATE_READY     | 0               |
    |   157     |   154    | DEV_BOARD0_TIMER_IO6_IN                                                    | CLK_STATE_READY     | 0               |
    |   157     |   155    | DEV_BOARD0_TIMER_IO7_IN                                                    | CLK_STATE_READY     | 0               |
    |   157     |   156    | DEV_BOARD0_TRC_CLK_IN                                                      | CLK_STATE_READY     | 0               |
    |   157     |   157    | DEV_BOARD0_VOUT0_EXTPCLKIN_OUT                                             | CLK_STATE_READY     | 0               |
    |   157     |   158    | DEV_BOARD0_VOUT0_PCLK_IN                                                   | CLK_STATE_READY     | 0               |
    |   157     |   159    | DEV_BOARD0_WKUP_CLKOUT0_IN                                                 | CLK_STATE_NOT_READY | 0               |
    |   157     |   160    | DEV_BOARD0_WKUP_CLKOUT0_IN_PARENT_WKUP_CLKOUT_SEL_OUT0                     | CLK_STATE_NOT_READY | 0               |
    |   157     |   161    | DEV_BOARD0_WKUP_CLKOUT0_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT                  | CLK_STATE_READY     | 25000000        |
    |-------------------------------------------------------------------------------------------------------------------------------------------|
    

    k3conf dump clock 191:

    |------------------------------------------------------------------------------|
    | VERSION INFO                                                                 |
    |------------------------------------------------------------------------------|
    | K3CONF | (version 0.3-nogit built Fri Oct 06 12:20:16 UTC 2023)              |
    | SoC    | AM62Ax SR1.0                                                        |
    | SYSFW  | ABI: 3.1 (firmware version 0x0009 '9.1.8--v09.01.08 (Kool Koala))') |
    |------------------------------------------------------------------------------|
    
    |-----------------------------------------------------------------------------------------------------------------------------|
    | Device ID | Clock ID | Clock Name                                                       | Status          | Clock Frequency |
    |-----------------------------------------------------------------------------------------------------------------------------|
    |   191     |     0    | DEV_MCASP1_AUX_CLK                                               | CLK_STATE_READY | 100000000       |
    |   191     |     1    | DEV_MCASP1_AUX_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT8_CLK     | CLK_STATE_READY | 100000000       |
    |   191     |     2    | DEV_MCASP1_AUX_CLK_PARENT_POSTDIV1_16FFT_MAIN_1_HSDIVOUT6_CLK    | CLK_STATE_READY | 96000000        |
    |   191     |     3    | DEV_MCASP1_MCASP_ACLKR_PIN                                       | CLK_STATE_READY | 0               |
    |   191     |     4    | DEV_MCASP1_MCASP_ACLKR_POUT                                      | CLK_STATE_READY | 0               |
    |   191     |     5    | DEV_MCASP1_MCASP_ACLKX_PIN                                       | CLK_STATE_READY | 0               |
    |   191     |     6    | DEV_MCASP1_MCASP_ACLKX_POUT                                      | CLK_STATE_READY | 0               |
    |   191     |     7    | DEV_MCASP1_MCASP_AFSR_POUT                                       | CLK_STATE_READY | 0               |
    |   191     |     8    | DEV_MCASP1_MCASP_AFSX_POUT                                       | CLK_STATE_READY | 0               |
    |   191     |     9    | DEV_MCASP1_MCASP_AHCLKR_PIN                                      | CLK_STATE_READY | 12288000        |
    |   191     |    10    | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_EXT_REFCLK1_OUT       | CLK_STATE_READY | 0               |
    |   191     |    11    | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT       | CLK_STATE_READY | 25000000        |
    |   191     |    12    | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT | CLK_STATE_READY | 0               |
    |   191     |    13    | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT | CLK_STATE_READY | 12288000        |
    |   191     |    14    | DEV_MCASP1_MCASP_AHCLKR_POUT                                     | CLK_STATE_READY | 0               |
    |   191     |    15    | DEV_MCASP1_MCASP_AHCLKX_PIN                                      | CLK_STATE_READY | 12288000        |
    |   191     |    16    | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_EXT_REFCLK1_OUT       | CLK_STATE_READY | 0               |
    |   191     |    17    | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT       | CLK_STATE_READY | 25000000        |
    |   191     |    18    | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT | CLK_STATE_READY | 0               |
    |   191     |    19    | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT | CLK_STATE_READY | 12288000        |
    |   191     |    20    | DEV_MCASP1_MCASP_AHCLKX_POUT                                     | CLK_STATE_READY | 0               |
    |   191     |    21    | DEV_MCASP1_VBUSP_CLK                                             | CLK_STATE_READY | 250000000       |
    |-----------------------------------------------------------------------------------------------------------------------------|
    

    k3conf dump device 191:

    |------------------------------------------------------------------------------|
    | VERSION INFO                                                                 |
    |------------------------------------------------------------------------------|
    | K3CONF | (version 0.3-nogit built Fri Oct 06 12:20:16 UTC 2023)              |
    | SoC    | AM62Ax SR1.0                                                        |
    | SYSFW  | ABI: 3.1 (firmware version 0x0009 '9.1.8--v09.01.08 (Kool Koala))') |
    |------------------------------------------------------------------------------|
    
    |-------------------------------------------------|
    | Device ID | Device Name       | Device Status   |
    |-------------------------------------------------|
    |   191     | AM62AX_DEV_MCASP1 | DEVICE_STATE_ON |
    |-------------------------------------------------|

    Register dump for McASP1:

    McASP1 registers: 
    /dev/mem opened.
    Memory mapped at address 0xffff9acde000.
    Read at address  0x02B10000 (0xffff9acde000): 0x44307B02
    /dev/mem opened.
    Memory mapped at address 0xffff9908f000.
    Read at address  0x02B10004 (0xffff9908f004): 0x00000002
    /dev/mem opened.
    Memory mapped at address 0xffff92297000.
    Read at address  0x02B10010 (0xffff92297010): 0x00000000
    /dev/mem opened.
    Memory mapped at address 0xffff8eeb6000.
    Read at address  0x02B10014 (0xffff8eeb6014): 0xBC000000
    /dev/mem opened.
    Memory mapped at address 0xffffa48c0000.
    Read at address  0x02B10018 (0xffffa48c0018): 0x00000000
    /dev/mem opened.
    Memory mapped at address 0xffff8eb1b000.
    Read at address  0x02B1001C (0xffff8eb1b01c): 0x10000004
    /dev/mem opened.
    Memory mapped at address 0xffffba116000.
    Read at address  0x02B10020 (0xffffba116020): 0x00000000
    /dev/mem opened.
    Memory mapped at address 0xffff9b27b000.
    Read at address  0x02B10044 (0xffff9b27b044): 0x0000131F
    /dev/mem opened.
    Memory mapped at address 0xffff8c9ca000.
    Read at address  0x02B10048 (0xffff8c9ca048): 0x00000000
    /dev/mem opened.
    Memory mapped at address 0xffffa2ef0000.
    Read at address  0x02B1004C (0xffffa2ef004c): 0x00000000
    /dev/mem opened.
    Memory mapped at address 0xffffa14a1000.
    Read at address  0x02B10050 (0xffffa14a1050): 0x00000000
    /dev/mem opened.
    Memory mapped at address 0xffff9fbd5000.
    Read at address  0x02B10060 (0xffff9fbd5060): 0x0000131F
    /dev/mem opened.
    Memory mapped at address 0xffffae37e000.
    Read at address  0x02B10064 (0xffffae37e064): 0xFFFFFFFF
    /dev/mem opened.
    Memory mapped at address 0xffff8f95e000.
    Read at address  0x02B10068 (0xffff8f95e068): 0x000180F0
    /dev/mem opened.
    Memory mapped at address 0xffff902f0000.
    Read at address  0x02B1006C (0xffff902f006c): 0x00000113
    /dev/mem opened.
    Memory mapped at address 0xffff95775000.
    Read at address  0x02B10070 (0xffff95775070): 0x000000A5
    /dev/mem opened.
    Memory mapped at address 0xfffface65000.
    Read at address  0x02B10074 (0xfffface65074): 0x00008000
    /dev/mem opened.
    Memory mapped at address 0xffff836cb000.
    Read at address  0x02B10078 (0xffff836cb078): 0x00000003
    /dev/mem opened.
    Memory mapped at address 0xffff8245d000.
    Read at address  0x02B1007C (0xffff8245d07c): 0x00000001
    /dev/mem opened.
    Memory mapped at address 0xffffa74a4000.
    Read at address  0x02B10080 (0xffffa74a4080): 0x0000015C
    /dev/mem opened.
    Memory mapped at address 0xffffb6c09000.
    Read at address  0x02B10084 (0xffffb6c09084): 0x00000001
    /dev/mem opened.
    Memory mapped at address 0xffffbdae3000.
    Read at address  0x02B10088 (0xffffbdae3088): 0x00000000
    /dev/mem opened.
    Memory mapped at address 0xffff8cf9d000.
    Read at address  0x02B1008C (0xffff8cf9d08c): 0x00000000
    /dev/mem opened.
    Memory mapped at address 0xffff95b0a000.
    Read at address  0x02B100A0 (0xffff95b0a0a0): 0x0000131F
    /dev/mem opened.
    Memory mapped at address 0xffffb7919000.
    Read at address  0x02B100A4 (0xffffb79190a4): 0xFFFFFFFF
    /dev/mem opened.
    Memory mapped at address 0xffff85a85000.
    Read at address  0x02B100A8 (0xffff85a850a8): 0x000100F0
    /dev/mem opened.
    Memory mapped at address 0xffffaa61c000.
    Read at address  0x02B100AC (0xffffaa61c0ac): 0x00000113
    /dev/mem opened.
    Memory mapped at address 0xffff98eaa000.
    Read at address  0x02B100B0 (0xffff98eaa0b0): 0x000000A5
    /dev/mem opened.
    Memory mapped at address 0xffff912cd000.
    Read at address  0x02B100B4 (0xffff912cd0b4): 0x00008000
    /dev/mem opened.
    Memory mapped at address 0xffffbb1e2000.
    Read at address  0x02B100B8 (0xffffbb1e20b8): 0x00000000
    /dev/mem opened.
    Memory mapped at address 0xffffa4fa3000.
    Read at address  0x02B100BC (0xffffa4fa30bc): 0x00000000
    /dev/mem opened.
    Memory mapped at address 0xffffa875c000.
    Read at address  0x02B100C0 (0xffffa875c0c0): 0x0000010C
    /dev/mem opened.
    Memory mapped at address 0xffff84b70000.
    Read at address  0x02B100C4 (0xffff84b700c4): 0x0000017F
    /dev/mem opened.
    Memory mapped at address 0xffff90b89000.
    Read at address  0x02B100C8 (0xffff90b890c8): 0x00000000
    /dev/mem opened.
    Memory mapped at address 0xffff9fb86000.
    Read at address  0x02B100CC (0xffff9fb860cc): 0x00000000
    /dev/mem opened.
    Memory mapped at address 0xffffb54a3000.
    Read at address  0x02B10100 (0xffffb54a3100): 0x00000000
    /dev/mem opened.
    Memory mapped at address 0xffff8c8ac000.
    Read at address  0x02B10104 (0xffff8c8ac104): 0x00000000
    /dev/mem opened.
    Memory mapped at address 0xffff9c042000.
    Read at address  0x02B10108 (0xffff9c042108): 0x00000000
    /dev/mem opened.
    Memory mapped at address 0xffffb776f000.
    Read at address  0x02B1010C (0xffffb776f10c): 0x00000000
    /dev/mem opened.
    Memory mapped at address 0xffffacd96000.
    Read at address  0x02B10110 (0xffffacd96110): 0x00000000
    /dev/mem opened.
    Memory mapped at address 0xffffb7329000.
    Read at address  0x02B10114 (0xffffb7329114): 0x00000000
    /dev/mem opened.
    Memory mapped at address 0xffff8fb2c000.
    Read at address  0x02B10118 (0xffff8fb2c118): 0x00000000
    /dev/mem opened.
    Memory mapped at address 0xffffa0a5f000.
    Read at address  0x02B1011C (0xffffa0a5f11c): 0x00000000
    /dev/mem opened.
    Memory mapped at address 0xffff8b265000.
    Read at address  0x02B10120 (0xffff8b265120): 0x00000000
    /dev/mem opened.
    Memory mapped at address 0xffffb3518000.
    Read at address  0x02B10124 (0xffffb3518124): 0x00000000
    /dev/mem opened.
    Memory mapped at address 0xffffa3309000.
    Read at address  0x02B10128 (0xffffa3309128): 0x00000000
    /dev/mem opened.
    Memory mapped at address 0xffff92ed8000.
    Read at address  0x02B1012C (0xffff92ed812c): 0x00000000
    /dev/mem opened.
    Memory mapped at address 0xffffa547b000.
    Read at address  0x02B10130 (0xffffa547b130): 0x00000000
    /dev/mem opened.
    Memory mapped at address 0xffff83817000.
    Read at address  0x02B10134 (0xffff83817134): 0x00000000
    /dev/mem opened.
    Memory mapped at address 0xffffa834c000.
    Read at address  0x02B10138 (0xffffa834c138): 0x00000000
    /dev/mem opened.
    Memory mapped at address 0xffffbdced000.
    Read at address  0x02B1013C (0xffffbdced13c): 0x00000000
    /dev/mem opened.
    Memory mapped at address 0xffffb5bec000.
    Read at address  0x02B10140 (0xffffb5bec140): 0x00000000
    /dev/mem opened.
    Memory mapped at address 0xffffbe64f000.
    Read at address  0x02B10144 (0xffffbe64f144): 0x00000000
    /dev/mem opened.
    Memory mapped at address 0xffffaef4e000.
    Read at address  0x02B10148 (0xffffaef4e148): 0x00000000
    /dev/mem opened.
    Memory mapped at address 0xffffb2ef2000.
    Read at address  0x02B1014C (0xffffb2ef214c): 0x00000000
    /dev/mem opened.
    Memory mapped at address 0xffffbdee1000.
    Read at address  0x02B10150 (0xffffbdee1150): 0x00000000
    /dev/mem opened.
    Memory mapped at address 0xffffb9206000.
    Read at address  0x02B10154 (0xffffb9206154): 0x00000000
    /dev/mem opened.
    Memory mapped at address 0xffff9ab05000.
    Read at address  0x02B10158 (0xffff9ab05158): 0x00000000
    /dev/mem opened.
    Memory mapped at address 0xffffb591d000.
    Read at address  0x02B1015C (0xffffb591d15c): 0x00000000
    /dev/mem opened.
    Memory mapped at address 0xffff817e2000.
    Read at address  0x02B10180 (0xffff817e2180): 0x00000008
    /dev/mem opened.
    Memory mapped at address 0xffffacfac000.
    Read at address  0x02B10184 (0xffffacfac184): 0x00000000
    /dev/mem opened.
    Memory mapped at address 0xffff93fde000.
    Read at address  0x02B10188 (0xffff93fde188): 0x00000002
    /dev/mem opened.
    Memory mapped at address 0xffffb508d000.
    Read at address  0x02B1018C (0xffffb508d18c): 0x00000000
    /dev/mem opened.
    Memory mapped at address 0xffffb9d96000.
    Read at address  0x02B10190 (0xffffb9d96190): 0x00000000
    /dev/mem opened.
    Memory mapped at address 0xffffb280b000.
    Read at address  0x02B10194 (0xffffb280b194): 0x00000000
    /dev/mem opened.
    Memory mapped at address 0xffffaa60c000.
    Read at address  0x02B10198 (0xffffaa60c198): 0x00000000
    /dev/mem opened.
    Memory mapped at address 0xffffb1ca9000.
    Read at address  0x02B1019C (0xffffb1ca919c): 0x00000000
    /dev/mem opened.
    Memory mapped at address 0xffff917a0000.
    Read at address  0x02B101A0 (0xffff917a01a0): 0x00000000
    /dev/mem opened.
    Memory mapped at address 0xffffba91d000.
    Read at address  0x02B101A4 (0xffffba91d1a4): 0x00000000
    /dev/mem opened.
    Memory mapped at address 0xffff96cc9000.
    Read at address  0x02B101A8 (0xffff96cc91a8): 0x00000000
    /dev/mem opened.
    Memory mapped at address 0xffff88c4a000.
    Read at address  0x02B101AC (0xffff88c4a1ac): 0x00000000
    /dev/mem opened.
    Memory mapped at address 0xffffbc0d9000.
    Read at address  0x02B101B0 (0xffffbc0d91b0): 0x00000000
    /dev/mem opened.
    Memory mapped at address 0xffffaa681000.
    Read at address  0x02B101B4 (0xffffaa6811b4): 0x00000000
    /dev/mem opened.
    Memory mapped at address 0xffff84867000.
    Read at address  0x02B101B8 (0xffff848671b8): 0x00000000
    /dev/mem opened.
    Memory mapped at address 0xffffae878000.
    Read at address  0x02B101BC (0xffffae8781bc): 0x00000000
    /dev/mem opened.
    Memory mapped at address 0xffff9d429000.
    Read at address  0x02B11000 (0xffff9d429000): 0x00007B02
    /dev/mem opened.
    Memory mapped at address 0xffff889d5000.
    Read at address  0x02B11004 (0xffff889d5004): 0x00000000
    /dev/mem opened.
    Memory mapped at address 0xffff848d7000.
    Read at address  0x02B11008 (0xffff848d7008): 0x00012001
    /dev/mem opened.
    Memory mapped at address 0xffffa9b33000.
    Read at address  0x02B1100C (0xffffa9b3300c): 0x00000012

    With this device tree I see a 16.666 MHz clock for the bitclock (instead of the 2.024 MHz bitclock I would expect).

    Regards,

    Bas Vermeulen

  • Hi Bas,

    See the below diagram (from TRM)

    From what you have shared, I infer that

    /dev/mem opened.
    Memory mapped at address 0xffff95775000.
    Read at address 0x02B10070 (0xffff95775070): 0x000000A5

    The CLKRDIV is dividing the incoming clock by 6. 

    Also AHCLKRCTL 

    Memory mapped at address 0xfffface65000.
    Read at address 0x02B10074 (0xfffface65074): 0x00008000 

    This is a reset value and I think its not receiving the Master clock correctly, which in your case should have been 12288000.

    Best Regards,

    Suren

  • Hi Suren,

    Is it possible to use this crystal from the EVB (PROC135A_SCH.pdf page 40)

    connected to this pin (PROC135A_SCH.pdf page 32)

    as an incoming AUDIO_EXT_REFCLK1 for McASP1? I'm guessing the device tree pinmux needs to be changed to allow the use. 

    And once that is connected, how do I configure the device tree to introduce AUDIO_EXT_REFCLK1 with a clock rate of 12.288 MHz?

    I think that since the pin for AUDIO_EXT_REFCLK1 isn't configured in the pinmux, the AUDIO_EXT_REFCLK1 signal is coming from DEV_BOARD0_AUDIO_EXT_REFCLK1_IN (which is set to 100 MHz), which would explain the 16.666 MHz clock I see instead of the 2.048 MHz clock I expect.

    If I configure the pinmux for pin A20 to be an input and configured as AUDIO_EXT_REFCLK1, will this work as expected?

    Regards,

    Bas Vermeulen

  • as an incoming AUDIO_EXT_REFCLK1 for McASP1? I'm guessing the device tree pinmux needs to be changed to allow the use. 

    Yes, you need to ensure the pinmux is configured correctly.  I used the Sysconfig tool to generate the following example:

    /* This file was auto-generated by TI PinMux on 3/6/2024 at 8:51:31 AM. */
    /* This file should only be used as a reference. Some pins/peripherals, */
    /* depending on your use case, may need additional configuration. */

    &main_pmx0 {
       audio_ext_refclk1_example_pins_default: audio_ext_refclk1_example-default-pins {
          pinctrl-single,pins = <
             AM62AX_IOPAD(0x01a8, PIN_INPUT, 2) /* (A20) MCASP0_AFSX.AUDIO_EXT_REFCLK1 */
          >;
       };
    };

    If I configure the pinmux for pin A20 to be an input and configured as AUDIO_EXT_REFCLK1, will this work as expected?

    Assuming you have the muxes and divider in the clock path configured correctly, I would expect you to get the correct bit clock frequency. 

    Here's a summary of what think you are using (excluding the pinmux) 

    And once that is connected, how do I configure the device tree to introduce AUDIO_EXT_REFCLK1 with a clock rate of 12.288 MHz?

    Suren should be able to help with this

  • Hi Paul,

    I have modified my device tree overlay to the following:

    // SPDX-License-Identifier: GPL-2.0
    /**
     * Audio recording via ICS43432 for AM625-SK and AM62-LP SK.
     *
     * Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/
     */
    
    /dts-v1/;
    /plugin/;
    
    #include "k3-pinctrl.h"
    
    &{/} {
    	audio_ext_refclk1: clock {
    		compatible = "ti,am62-audio-refclk";
    		#clock-cells = <0>;
    		clocks = <&k3_clks 157 19>;
    		assigned-clocks = <&k3_clks 157 19>;
    		assigned-clock-rates = <12288000>;
    	};
    	
    	ics43432: card-codec {
    		#sound-dai-cells = <0>;
    		compatible = "invensense,ics43432";
    		status = "okay";
    	};
    
    	ics43432_audio: sound-ics43432 {
    		compatible = "simple-audio-card";
    		simple-audio-card,name = "AM62x-ICS43432";
    		simple-audio-card,format = "i2s";
    		simple-audio-card,bitclock-master = <&mic_dailink_master>;
    		simple-audio-card,frame-master = <&mic_dailink_master>;
    		mic_dailink_master: simple-audio-card,cpu {
    			sound-dai = <&mcasp1>;
    			system-clock-direction-out;
    		};
    		simple-audio-card,codec {
    			sound-dai = <&ics43432>;
    		};
    	};
    };
    
    &mcasp1 {
    	pinctrl-0 = <&main_mcasp1_pins_default>, <&audio_ext_refclk1_pins_default>;
    	clocks = <&k3_clks 191 9>, <&k3_clks 191 15>;
    	assigned-clocks = <&k3_clks 191 9>, <&k3_clks 191 15>;
    	assigned-clock-parents = <&k3_clks 191 13>, <&k3_clks 191 19>;
    };
    
    &main_pmx0 {
       audio_ext_refclk1_pins_default: audio-ext-refclk1-pins-default {
          pinctrl-single,pins = <
             AM62AX_IOPAD(0x01a8, PIN_INPUT, 2) /* (A20) MCASP0_AFSX.AUDIO_EXT_REFCLK1 */
          >;
       };
    };
    
    &codec_audio {
    	status = "disabled";
    };
    
    &tlv320aic3106 {
    	status = "disabled";
    };
    
    &tlv320_mclk {
    	status = "disabled";
    };
    

    The pinctrl definition is created, and added to mcasp1's pinctrl-0. I see it as active, and pin 106 is configured with the value 00050002 (I believe that's INPUT and PULL_DISABLE, function 2):

    pin 106 (PIN106) 0:? f41a8 00050002 pinctrl-single

    I get the following while arecord is actively recording (k3conf dump clock of the relevant clocks, and devmem2 read of the mcasp1 registers):

    |------------------------------------------------------------------------------|
    | VERSION INFO                                                                 |
    |------------------------------------------------------------------------------|
    | K3CONF | (version 0.3-nogit built Fri Oct 06 12:20:16 UTC 2023)              |
    | SoC    | AM62Ax SR1.0                                                        |
    | SYSFW  | ABI: 3.1 (firmware version 0x0009 '9.1.8--v09.01.08 (Kool Koala))') |
    |------------------------------------------------------------------------------|
    
    |-------------------------------------------------------------------------------------------------------------------------------------------|
    | Device ID | Clock ID | Clock Name                                                                 | Status              | Clock Frequency |
    |-------------------------------------------------------------------------------------------------------------------------------------------|
    |   157     |     0    | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN                                            | CLK_STATE_READY     | 100000000       |
    |   157     |     1    | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT      | CLK_STATE_NOT_READY | 0               |
    |   157     |     2    | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT      | CLK_STATE_READY     | 0               |
    |   157     |     3    | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT      | CLK_STATE_NOT_READY | 0               |
    |   157     |     4    | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT      | CLK_STATE_NOT_READY | 0               |
    |   157     |     5    | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT      | CLK_STATE_READY     | 0               |
    |   157     |     6    | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT      | CLK_STATE_NOT_READY | 0               |
    |   157     |     7    | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_POSTDIV1_16FFT_MAIN_1_HSDIVOUT6_CLK | CLK_STATE_READY     | 96000000        |
    |   157     |     8    | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT8_CLK  | CLK_STATE_READY     | 100000000       |
    |   157     |     9    | DEV_BOARD0_AUDIO_EXT_REFCLK0_OUT                                           | CLK_STATE_READY     | 0               |
    |   157     |    10    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN                                            | CLK_STATE_READY     | 100000000       |
    |   157     |    11    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT      | CLK_STATE_NOT_READY | 0               |
    |   157     |    12    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT      | CLK_STATE_READY     | 0               |
    |   157     |    13    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT      | CLK_STATE_NOT_READY | 0               |
    |   157     |    14    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT      | CLK_STATE_NOT_READY | 0               |
    |   157     |    15    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT      | CLK_STATE_READY     | 0               |
    |   157     |    16    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT      | CLK_STATE_NOT_READY | 0               |
    |   157     |    17    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_POSTDIV1_16FFT_MAIN_1_HSDIVOUT6_CLK | CLK_STATE_READY     | 96000000        |
    |   157     |    18    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT8_CLK  | CLK_STATE_READY     | 100000000       |
    |   157     |    19    | DEV_BOARD0_AUDIO_EXT_REFCLK1_OUT                                           | CLK_STATE_READY     | 12288000        |
    |   157     |    20    | DEV_BOARD0_CLKOUT0_IN                                                      | CLK_STATE_READY     | 50000000        |
    |   157     |    21    | DEV_BOARD0_CLKOUT0_IN_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK5            | CLK_STATE_READY     | 50000000        |
    |   157     |    22    | DEV_BOARD0_CLKOUT0_IN_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK10           | CLK_STATE_READY     | 25000000        |
    |   157     |    23    | DEV_BOARD0_CP_GEMAC_CPTS0_RFT_CLK_OUT                                      | CLK_STATE_READY     | 0               |
    |   157     |    24    | DEV_BOARD0_DDR0_CK0_IN                                                     | CLK_STATE_READY     | 250000000       |
    |   157     |    25    | DEV_BOARD0_DDR0_CK0_N_IN                                                   | CLK_STATE_READY     | 0               |
    |   157     |    27    | DEV_BOARD0_DDR0_CK0_OUT                                                    | CLK_STATE_READY     | 0               |
    |   157     |    33    | DEV_BOARD0_EXT_REFCLK1_OUT                                                 | CLK_STATE_READY     | 0               |
    |   157     |    34    | DEV_BOARD0_GPMC0_CLKLB_IN                                                  | CLK_STATE_READY     | 0               |
    |   157     |    35    | DEV_BOARD0_GPMC0_CLKLB_OUT                                                 | CLK_STATE_READY     | 0               |
    |   157     |    36    | DEV_BOARD0_GPMC0_CLK_IN                                                    | CLK_STATE_READY     | 0               |
    |   157     |    37    | DEV_BOARD0_GPMC0_FCLK_MUX_IN                                               | CLK_STATE_READY     | 133333333       |
    |   157     |    38    | DEV_BOARD0_GPMC0_FCLK_MUX_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT3_CLK      | CLK_STATE_READY     | 133333333       |
    |   157     |    39    | DEV_BOARD0_GPMC0_FCLK_MUX_IN_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT7_CLK     | CLK_STATE_READY     | 100000000       |
    |   157     |    40    | DEV_BOARD0_I2C0_SCL_IN                                                     | CLK_STATE_READY     | 0               |
    |   157     |    41    | DEV_BOARD0_I2C0_SCL_OUT                                                    | CLK_STATE_READY     | 0               |
    |   157     |    42    | DEV_BOARD0_I2C1_SCL_IN                                                     | CLK_STATE_READY     | 0               |
    |   157     |    43    | DEV_BOARD0_I2C1_SCL_OUT                                                    | CLK_STATE_READY     | 0               |
    |   157     |    44    | DEV_BOARD0_I2C2_SCL_IN                                                     | CLK_STATE_READY     | 0               |
    |   157     |    45    | DEV_BOARD0_I2C2_SCL_OUT                                                    | CLK_STATE_READY     | 0               |
    |   157     |    46    | DEV_BOARD0_I2C3_SCL_IN                                                     | CLK_STATE_READY     | 0               |
    |   157     |    47    | DEV_BOARD0_I2C3_SCL_OUT                                                    | CLK_STATE_READY     | 0               |
    |   157     |    49    | DEV_BOARD0_MCASP0_ACLKR_IN                                                 | CLK_STATE_READY     | 0               |
    |   157     |    50    | DEV_BOARD0_MCASP0_ACLKR_OUT                                                | CLK_STATE_READY     | 0               |
    |   157     |    51    | DEV_BOARD0_MCASP0_ACLKX_IN                                                 | CLK_STATE_READY     | 0               |
    |   157     |    52    | DEV_BOARD0_MCASP0_ACLKX_OUT                                                | CLK_STATE_READY     | 0               |
    |   157     |    53    | DEV_BOARD0_MCASP0_AFSR_IN                                                  | CLK_STATE_READY     | 0               |
    |   157     |    54    | DEV_BOARD0_MCASP0_AFSX_IN                                                  | CLK_STATE_READY     | 0               |
    |   157     |    55    | DEV_BOARD0_MCASP1_ACLKR_IN                                                 | CLK_STATE_READY     | 0               |
    |   157     |    56    | DEV_BOARD0_MCASP1_ACLKR_OUT                                                | CLK_STATE_READY     | 0               |
    |   157     |    57    | DEV_BOARD0_MCASP1_ACLKX_IN                                                 | CLK_STATE_READY     | 0               |
    |   157     |    58    | DEV_BOARD0_MCASP1_ACLKX_OUT                                                | CLK_STATE_READY     | 0               |
    |   157     |    59    | DEV_BOARD0_MCASP1_AFSR_IN                                                  | CLK_STATE_READY     | 0               |
    |   157     |    60    | DEV_BOARD0_MCASP1_AFSX_IN                                                  | CLK_STATE_READY     | 0               |
    |   157     |    61    | DEV_BOARD0_MCASP2_ACLKR_IN                                                 | CLK_STATE_READY     | 0               |
    |   157     |    62    | DEV_BOARD0_MCASP2_ACLKR_OUT                                                | CLK_STATE_READY     | 0               |
    |   157     |    63    | DEV_BOARD0_MCASP2_ACLKX_IN                                                 | CLK_STATE_READY     | 0               |
    |   157     |    64    | DEV_BOARD0_MCASP2_ACLKX_OUT                                                | CLK_STATE_READY     | 0               |
    |   157     |    65    | DEV_BOARD0_MCASP2_AFSR_IN                                                  | CLK_STATE_READY     | 0               |
    |   157     |    66    | DEV_BOARD0_MCASP2_AFSX_IN                                                  | CLK_STATE_READY     | 0               |
    |   157     |    67    | DEV_BOARD0_MCU_EXT_REFCLK0_OUT                                             | CLK_STATE_READY     | 0               |
    |   157     |    69    | DEV_BOARD0_MCU_I2C0_SCL_OUT                                                | CLK_STATE_READY     | 0               |
    |   157     |    70    | DEV_BOARD0_MCU_OBSCLK0_IN                                                  | CLK_STATE_READY     | 12500000        |
    |   157     |    71    | DEV_BOARD0_MCU_OBSCLK0_IN_PARENT_MCU_OBSCLK_DIV_OUT0                       | CLK_STATE_READY     | 12500000        |
    |   157     |    72    | DEV_BOARD0_MCU_OBSCLK0_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT                   | CLK_STATE_READY     | 25000000        |
    |   157     |    73    | DEV_BOARD0_MCU_SPI0_CLK_IN                                                 | CLK_STATE_READY     | 0               |
    |   157     |    74    | DEV_BOARD0_MCU_SPI0_CLK_OUT                                                | CLK_STATE_READY     | 0               |
    |   157     |    75    | DEV_BOARD0_MCU_SPI1_CLK_IN                                                 | CLK_STATE_READY     | 0               |
    |   157     |    76    | DEV_BOARD0_MCU_SPI1_CLK_OUT                                                | CLK_STATE_READY     | 0               |
    |   157     |    77    | DEV_BOARD0_MCU_SYSCLKOUT0_IN                                               | CLK_STATE_READY     | 100000000       |
    |   157     |    78    | DEV_BOARD0_MCU_TIMER_IO0_IN                                                | CLK_STATE_READY     | 0               |
    |   157     |    79    | DEV_BOARD0_MCU_TIMER_IO1_IN                                                | CLK_STATE_READY     | 0               |
    |   157     |    80    | DEV_BOARD0_MCU_TIMER_IO2_IN                                                | CLK_STATE_READY     | 0               |
    |   157     |    81    | DEV_BOARD0_MCU_TIMER_IO3_IN                                                | CLK_STATE_READY     | 0               |
    |   157     |    82    | DEV_BOARD0_MDIO0_MDC_IN                                                    | CLK_STATE_READY     | 0               |
    |   157     |    83    | DEV_BOARD0_MMC0_CLKLB_IN                                                   | CLK_STATE_READY     | 0               |
    |   157     |    84    | DEV_BOARD0_MMC0_CLKLB_OUT                                                  | CLK_STATE_READY     | 0               |
    |   157     |    85    | DEV_BOARD0_MMC0_CLK_IN                                                     | CLK_STATE_READY     | 0               |
    |   157     |    86    | DEV_BOARD0_MMC0_CLK_OUT                                                    | CLK_STATE_READY     | 0               |
    |   157     |    87    | DEV_BOARD0_MMC1_CLKLB_IN                                                   | CLK_STATE_READY     | 0               |
    |   157     |    88    | DEV_BOARD0_MMC1_CLKLB_OUT                                                  | CLK_STATE_READY     | 0               |
    |   157     |    89    | DEV_BOARD0_MMC1_CLK_IN                                                     | CLK_STATE_READY     | 0               |
    |   157     |    90    | DEV_BOARD0_MMC1_CLK_OUT                                                    | CLK_STATE_READY     | 0               |
    |   157     |    91    | DEV_BOARD0_MMC2_CLKLB_IN                                                   | CLK_STATE_READY     | 0               |
    |   157     |    92    | DEV_BOARD0_MMC2_CLKLB_OUT                                                  | CLK_STATE_READY     | 0               |
    |   157     |    93    | DEV_BOARD0_MMC2_CLK_IN                                                     | CLK_STATE_READY     | 0               |
    |   157     |    94    | DEV_BOARD0_MMC2_CLK_OUT                                                    | CLK_STATE_READY     | 0               |
    |   157     |    95    | DEV_BOARD0_OBSCLK0_IN                                                      | CLK_STATE_READY     | 500000000       |
    |   157     |    96    | DEV_BOARD0_OBSCLK0_IN_PARENT_MAIN_OBSCLK_DIV_OUT0                          | CLK_STATE_READY     | 500000000       |
    |   157     |    97    | DEV_BOARD0_OBSCLK0_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT                       | CLK_STATE_READY     | 25000000        |
    |   157     |   128    | DEV_BOARD0_OBSCLK1_IN                                                      | CLK_STATE_READY     | 500000000       |
    |   157     |   129    | DEV_BOARD0_OSPI0_DQS_OUT                                                   | CLK_STATE_READY     | 0               |
    |   157     |   130    | DEV_BOARD0_OSPI0_LBCLKO_IN                                                 | CLK_STATE_READY     | 0               |
    |   157     |   131    | DEV_BOARD0_OSPI0_LBCLKO_OUT                                                | CLK_STATE_READY     | 0               |
    |   157     |   132    | DEV_BOARD0_RGMII1_RXC_OUT                                                  | CLK_STATE_READY     | 0               |
    |   157     |   133    | DEV_BOARD0_RGMII1_TXC_IN                                                   | CLK_STATE_READY     | 0               |
    |   157     |   134    | DEV_BOARD0_RGMII1_TXC_OUT                                                  | CLK_STATE_READY     | 0               |
    |   157     |   135    | DEV_BOARD0_RGMII2_RXC_OUT                                                  | CLK_STATE_READY     | 0               |
    |   157     |   136    | DEV_BOARD0_RGMII2_TXC_IN                                                   | CLK_STATE_READY     | 0               |
    |   157     |   137    | DEV_BOARD0_RGMII2_TXC_OUT                                                  | CLK_STATE_READY     | 0               |
    |   157     |   138    | DEV_BOARD0_RMII1_REF_CLK_OUT                                               | CLK_STATE_READY     | 0               |
    |   157     |   139    | DEV_BOARD0_RMII2_REF_CLK_OUT                                               | CLK_STATE_READY     | 0               |
    |   157     |   140    | DEV_BOARD0_SPI0_CLK_IN                                                     | CLK_STATE_READY     | 0               |
    |   157     |   141    | DEV_BOARD0_SPI0_CLK_OUT                                                    | CLK_STATE_READY     | 0               |
    |   157     |   142    | DEV_BOARD0_SPI1_CLK_IN                                                     | CLK_STATE_READY     | 0               |
    |   157     |   143    | DEV_BOARD0_SPI1_CLK_OUT                                                    | CLK_STATE_READY     | 0               |
    |   157     |   144    | DEV_BOARD0_SPI2_CLK_IN                                                     | CLK_STATE_READY     | 0               |
    |   157     |   145    | DEV_BOARD0_SPI2_CLK_OUT                                                    | CLK_STATE_READY     | 0               |
    |   157     |   146    | DEV_BOARD0_SYSCLKOUT0_IN                                                   | CLK_STATE_READY     | 125000000       |
    |   157     |   147    | DEV_BOARD0_TCK_OUT                                                         | CLK_STATE_READY     | 0               |
    |   157     |   148    | DEV_BOARD0_TIMER_IO0_IN                                                    | CLK_STATE_READY     | 0               |
    |   157     |   149    | DEV_BOARD0_TIMER_IO1_IN                                                    | CLK_STATE_READY     | 0               |
    |   157     |   150    | DEV_BOARD0_TIMER_IO2_IN                                                    | CLK_STATE_READY     | 0               |
    |   157     |   151    | DEV_BOARD0_TIMER_IO3_IN                                                    | CLK_STATE_READY     | 0               |
    |   157     |   152    | DEV_BOARD0_TIMER_IO4_IN                                                    | CLK_STATE_READY     | 0               |
    |   157     |   153    | DEV_BOARD0_TIMER_IO5_IN                                                    | CLK_STATE_READY     | 0               |
    |   157     |   154    | DEV_BOARD0_TIMER_IO6_IN                                                    | CLK_STATE_READY     | 0               |
    |   157     |   155    | DEV_BOARD0_TIMER_IO7_IN                                                    | CLK_STATE_READY     | 0               |
    |   157     |   156    | DEV_BOARD0_TRC_CLK_IN                                                      | CLK_STATE_READY     | 0               |
    |   157     |   157    | DEV_BOARD0_VOUT0_EXTPCLKIN_OUT                                             | CLK_STATE_READY     | 0               |
    |   157     |   158    | DEV_BOARD0_VOUT0_PCLK_IN                                                   | CLK_STATE_READY     | 0               |
    |   157     |   159    | DEV_BOARD0_WKUP_CLKOUT0_IN                                                 | CLK_STATE_NOT_READY | 0               |
    |   157     |   160    | DEV_BOARD0_WKUP_CLKOUT0_IN_PARENT_WKUP_CLKOUT_SEL_OUT0                     | CLK_STATE_NOT_READY | 0               |
    |   157     |   161    | DEV_BOARD0_WKUP_CLKOUT0_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT                  | CLK_STATE_READY     | 25000000        |
    |-------------------------------------------------------------------------------------------------------------------------------------------|
    
    |------------------------------------------------------------------------------|
    | VERSION INFO                                                                 |
    |------------------------------------------------------------------------------|
    | K3CONF | (version 0.3-nogit built Fri Oct 06 12:20:16 UTC 2023)              |
    | SoC    | AM62Ax SR1.0                                                        |
    | SYSFW  | ABI: 3.1 (firmware version 0x0009 '9.1.8--v09.01.08 (Kool Koala))') |
    |------------------------------------------------------------------------------|
    
    |-----------------------------------------------------------------------------------------------------------------------------|
    | Device ID | Clock ID | Clock Name                                                       | Status          | Clock Frequency |
    |-----------------------------------------------------------------------------------------------------------------------------|
    |   191     |     0    | DEV_MCASP1_AUX_CLK                                               | CLK_STATE_READY | 100000000       |
    |   191     |     1    | DEV_MCASP1_AUX_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT8_CLK     | CLK_STATE_READY | 100000000       |
    |   191     |     2    | DEV_MCASP1_AUX_CLK_PARENT_POSTDIV1_16FFT_MAIN_1_HSDIVOUT6_CLK    | CLK_STATE_READY | 96000000        |
    |   191     |     3    | DEV_MCASP1_MCASP_ACLKR_PIN                                       | CLK_STATE_READY | 0               |
    |   191     |     4    | DEV_MCASP1_MCASP_ACLKR_POUT                                      | CLK_STATE_READY | 0               |
    |   191     |     5    | DEV_MCASP1_MCASP_ACLKX_PIN                                       | CLK_STATE_READY | 0               |
    |   191     |     6    | DEV_MCASP1_MCASP_ACLKX_POUT                                      | CLK_STATE_READY | 0               |
    |   191     |     7    | DEV_MCASP1_MCASP_AFSR_POUT                                       | CLK_STATE_READY | 0               |
    |   191     |     8    | DEV_MCASP1_MCASP_AFSX_POUT                                       | CLK_STATE_READY | 0               |
    |   191     |     9    | DEV_MCASP1_MCASP_AHCLKR_PIN                                      | CLK_STATE_READY | 12288000        |
    |   191     |    10    | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_EXT_REFCLK1_OUT       | CLK_STATE_READY | 0               |
    |   191     |    11    | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT       | CLK_STATE_READY | 25000000        |
    |   191     |    12    | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT | CLK_STATE_READY | 0               |
    |   191     |    13    | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT | CLK_STATE_READY | 12288000        |
    |   191     |    14    | DEV_MCASP1_MCASP_AHCLKR_POUT                                     | CLK_STATE_READY | 0               |
    |   191     |    15    | DEV_MCASP1_MCASP_AHCLKX_PIN                                      | CLK_STATE_READY | 12288000        |
    |   191     |    16    | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_EXT_REFCLK1_OUT       | CLK_STATE_READY | 0               |
    |   191     |    17    | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT       | CLK_STATE_READY | 25000000        |
    |   191     |    18    | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT | CLK_STATE_READY | 0               |
    |   191     |    19    | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT | CLK_STATE_READY | 12288000        |
    |   191     |    20    | DEV_MCASP1_MCASP_AHCLKX_POUT                                     | CLK_STATE_READY | 0               |
    |   191     |    21    | DEV_MCASP1_VBUSP_CLK                                             | CLK_STATE_READY | 250000000       |
    |-----------------------------------------------------------------------------------------------------------------------------|
    
    |------------------------------------------------------------------------------|
    | VERSION INFO                                                                 |
    |------------------------------------------------------------------------------|
    | K3CONF | (version 0.3-nogit built Fri Oct 06 12:20:16 UTC 2023)              |
    | SoC    | AM62Ax SR1.0                                                        |
    | SYSFW  | ABI: 3.1 (firmware version 0x0009 '9.1.8--v09.01.08 (Kool Koala))') |
    |------------------------------------------------------------------------------|
    
    |-------------------------------------------------|
    | Device ID | Device Name       | Device Status   |
    |-------------------------------------------------|
    |   191     | AM62AX_DEV_MCASP1 | DEVICE_STATE_ON |
    |-------------------------------------------------|
    
    McASP1 registers: 
    Read at address  0x02B10000 (0xffff8ec49000): 0x44307B02
    Read at address  0x02B10004 (0xffffac3b5004): 0x00000002
    Read at address  0x02B10010 (0xffffaf71a010): 0x00000000
    Read at address  0x02B10014 (0xffffaf7b3014): 0xBC000000
    Read at address  0x02B10018 (0xffff80b76018): 0x00000000
    Read at address  0x02B1001C (0xffff958f201c): 0x04000004
    Read at address  0x02B10020 (0xffffbbf71020): 0x00000000
    Read at address  0x02B10044 (0xffffa957f044): 0x0000131F
    Read at address  0x02B10048 (0xffff98b4e048): 0x00000000
    Read at address  0x02B1004C (0xffffba7a404c): 0x00000000
    Read at address  0x02B10050 (0xffff8e754050): 0x00000000
    Read at address  0x02B10060 (0xffff89a0e060): 0x0000131F
    Read at address  0x02B10064 (0xffffae270064): 0xFFFFFFFF
    Read at address  0x02B10068 (0xffff9df13068): 0x000180F0
    Read at address  0x02B1006C (0xffffb814206c): 0x00000113
    Read at address  0x02B10070 (0xffff98228070): 0x000000A5
    Read at address  0x02B10074 (0xffff89ed8074): 0x00008000
    Read at address  0x02B10078 (0xffffa6db6078): 0x00000003
    Read at address  0x02B1007C (0xffff8300707c): 0x00000001
    Read at address  0x02B10080 (0xffffa3ec4080): 0x0000015C
    Read at address  0x02B10084 (0xffff880a7084): 0x00000000
    Read at address  0x02B10088 (0xffffa2cfa088): 0x8A000000
    Read at address  0x02B1008C (0xffffb98d208c): 0x00000000
    Read at address  0x02B100A0 (0xffffbb7240a0): 0x0000131F
    Read at address  0x02B100A4 (0xffffa1a030a4): 0xFFFFFFFF
    Read at address  0x02B100A8 (0xffff80d200a8): 0x000100F0
    Read at address  0x02B100AC (0xffff9f9140ac): 0x00000113
    Read at address  0x02B100B0 (0xffffb382d0b0): 0x000000A5
    Read at address  0x02B100B4 (0xffffbd40c0b4): 0x00008000
    Read at address  0x02B100B8 (0xffff908e40b8): 0x00000000
    Read at address  0x02B100BC (0xffff9c2d20bc): 0x00000000
    Read at address  0x02B100C0 (0xffff85d890c0): 0x0000010C
    Read at address  0x02B100C4 (0xffffb1f240c4): 0x0000017F
    Read at address  0x02B100C8 (0xffffbbc220c8): 0x8A000000
    Read at address  0x02B100CC (0xffff8ef400cc): 0x00000000
    Read at address  0x02B10100 (0xffffa7bf4100): 0x00000000
    Read at address  0x02B10104 (0xffffb185e104): 0x00000000
    Read at address  0x02B10108 (0xffffa414f108): 0x00000000
    Read at address  0x02B1010C (0xffff925b810c): 0x00000000
    Read at address  0x02B10110 (0xffff903c3110): 0x00000000
    Read at address  0x02B10114 (0xffff8ba5f114): 0x00000000
    Read at address  0x02B10118 (0xffffac7c7118): 0x00000000
    Read at address  0x02B1011C (0xffffb565811c): 0x00000000
    Read at address  0x02B10120 (0xffffbe9f6120): 0x00000000
    Read at address  0x02B10124 (0xffff8316c124): 0x00000000
    Read at address  0x02B10128 (0xffff82b35128): 0x00000000
    Read at address  0x02B1012C (0xffffb741212c): 0x00000000
    Read at address  0x02B10130 (0xffff97bb7130): 0x00000000
    Read at address  0x02B10134 (0xffffb6c1f134): 0x00000000
    Read at address  0x02B10138 (0xffffb0f98138): 0x00000000
    Read at address  0x02B1013C (0xffff985c013c): 0x00000000
    Read at address  0x02B10140 (0xffffa1aca140): 0x00000000
    Read at address  0x02B10144 (0xffffac182144): 0x00000000
    Read at address  0x02B10148 (0xffffb9b03148): 0x00000000
    Read at address  0x02B1014C (0xffffacbb214c): 0x00000000
    Read at address  0x02B10150 (0xffff8dcc1150): 0x00000000
    Read at address  0x02B10154 (0xffff9344b154): 0x00000000
    Read at address  0x02B10158 (0xffff9d623158): 0x00000000
    Read at address  0x02B1015C (0xffff89ff615c): 0x00000000
    Read at address  0x02B10180 (0xffffa9430180): 0x00000008
    Read at address  0x02B10184 (0xffff894a3184): 0x00000000
    Read at address  0x02B10188 (0xffffa7dd1188): 0x00000002
    Read at address  0x02B1018C (0xffffb8d6b18c): 0x00000000
    Read at address  0x02B10190 (0xffffad6b4190): 0x00000000
    Read at address  0x02B10194 (0xffffb0f59194): 0x00000000
    Read at address  0x02B10198 (0xffff84264198): 0x00000000
    Read at address  0x02B1019C (0xffff824db19c): 0x00000000
    Read at address  0x02B101A0 (0xffff96dae1a0): 0x00000000
    Read at address  0x02B101A4 (0xffff9bdf31a4): 0x00000000
    Read at address  0x02B101A8 (0xffffa3c9b1a8): 0x00000000
    Read at address  0x02B101AC (0xffffafefc1ac): 0x00000000
    Read at address  0x02B101B0 (0xffffa4e711b0): 0x00000000
    Read at address  0x02B101B4 (0xffff85d151b4): 0x00000000
    Read at address  0x02B101B8 (0xffff8d11e1b8): 0x00000000
    Read at address  0x02B101BC (0xffff8051e1bc): 0x00000000
    Read at address  0x02B11000 (0xffffb74c7000): 0x00007B02
    Read at address  0x02B11004 (0xffff9b64f004): 0x00000000
    Read at address  0x02B11008 (0xffff9138e008): 0x00012001
    Read at address  0x02B1100C (0xffff854b700c): 0x00000012
    

    Unfortunately, the clock is still too fast, my arecord returns after about 8 seconds if I tell it to record 60 seconds.

    Regards,

    Bas Vermeulen

  • Is there a possibility that you provide an external clock instead and see the same behavior? Or increase the clock-frequency?

    Best Regards,

    Suren

  • I'm checking with my electronics people, I should have an answer/experiment done by Thursday.

    Bas

  • I just disabled the 12.288 MHz crystal (so no clock signal present) and was able to record the 60 seconds in the same 8.75 seconds.

    To me, that means the clock isn't being muxed correctly, and it is using some other clock. I'm just not sure which one, nor how to get the system to mux the correct one.

    Is there a way to check that the mux in question is set up correctly, apart from k3conf? As far as I can see, k3conf is saying that everything is as it should be, but the actual situation is different.

    Regards,

    Bas Vermeulen

  • I think I understand a little more. Page 5956 of the TRM shows the register to configure AUDIO_EXT_REFCLK1_OUT.

    The driver for this clock (drivers/clk/keystone/syscon-clk.c) only configures the outgoing clock (DEV_BOARD0_AUDIO_EXT_REFCLK1_IN),
    and enables/disables this clock with bit 15 of the register above. Bit 15 of that register sets the clock to input or output though. 

    |   157     |    10    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN                                            | CLK_STATE_READY     | 100000000       |
    |   157     |    11    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT      | CLK_STATE_NOT_READY | 0               |
    |   157     |    12    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT      | CLK_STATE_NOT_READY | 0               |
    |   157     |    13    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT      | CLK_STATE_NOT_READY | 0               |
    |   157     |    14    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT      | CLK_STATE_NOT_READY | 0               |
    |   157     |    15    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT      | CLK_STATE_NOT_READY | 0               |
    |   157     |    16    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT      | CLK_STATE_NOT_READY | 0               |
    |   157     |    17    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_POSTDIV1_16FFT_MAIN_1_HSDIVOUT6_CLK | CLK_STATE_READY     | 96000000        |
    |   157     |    18    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT8_CLK  | CLK_STATE_READY     | 100000000       |
    |   157     |    19    | DEV_BOARD0_AUDIO_EXT_REFCLK1_OUT                                           | CLK_STATE_READY     | 12288000        |

    Am I correct in the interpretation that if bit 15 of 0x1082e4 is 0, DEV_BOARD0_AUDIO_EXT_REFCLK1_OUT is active, and if that bit is 1, DEV_BOARD0_AUDIO_EXT_REFCLK1_IN is active?

    Is there a way to enable the DEV_BOARD0_AUDIO_EXT_REFCLK1_OUT clock? According to the regmap the clock is already set to input (the value is 00000007, meaning bit 15 is off); I still don't see the correct clock rate used by McASP1.

  • I finally got it working. When using the following device tree overlay, I get the correct bitclock, derived from the 12.288 MHz crystal connected to AUDIO_EXT_REFCLK1:

    // SPDX-License-Identifier: GPL-2.0
    /**
     * Audio recording via ICS43432 for AM625-SK and AM62-LP SK.
     *
     * Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/
     */
    
    /dts-v1/;
    /plugin/;
    
    #include "k3-pinctrl.h"
    
    &{/} {
    	ics43432: card-codec {
    		#sound-dai-cells = <0>;
    		compatible = "invensense,ics43432";
    		status = "okay";
    	};
    
    	ics43432_audio: sound-ics43432 {
    		compatible = "simple-audio-card";
    		simple-audio-card,name = "AM62x-ICS43432";
    		simple-audio-card,format = "i2s";
    		simple-audio-card,bitclock-master = <&mic_dailink_master>;
    		simple-audio-card,frame-master = <&mic_dailink_master>;
    		mic_dailink_master: simple-audio-card,cpu {
    			clocks = <&k3_clks 157 19>;
    			dai-tdm-slot-num = <2>;
    			dai-tdm-slot-width = <32>;
    			sound-dai = <&mcasp1>;
    		};
    		simple-audio-card,codec {
    			sound-dai = <&ics43432>;
    			dai-tdm-slot-num = <2>;
    			dai-tdm-slot-width = <32>;
    		};
    	};
    };
    
    &mcasp1 {
    	pinctrl-0 = <&main_mcasp1_pins_default>, <&audio_ext_refclk1_pins_default>;
    	clock-names = "ahclkr", "ahclkx", "fck", "audio_ext_refclk1";
    	clocks = <&k3_clks 191 9>, <&k3_clks 191 15>, <&k3_clks 191 0>, <&k3_clks 157 19>;
    	assigned-clocks = <&k3_clks 191 9>, <&k3_clks 191 15>, <&k3_clks 191 0>, <&k3_clks 157 19>;
    	assigned-clock-parents = <&k3_clks 191 13>, <&k3_clks 191 19>, <&k3_clks 191 2>;
    	assigned-clock-rates = <12288000>, <12288000>, <96000000>, <12288000>;
    };
    
    &main_pmx0 {
       audio_ext_refclk1_pins_default: audio-ext-refclk1-pins-default {
          pinctrl-single,pins = <
             AM62AX_IOPAD(0x01a8, PIN_INPUT, 2) /* (A20) MCASP0_AFSX.AUDIO_EXT_REFCLK1 */
          >;
       };
    };
    
    &codec_audio {
    	status = "disabled";
    };
    
    &tlv320aic3106 {
    	status = "disabled";
    };
    
    &tlv320_mclk {
    	status = "disabled";
    };
    
    &audio_refclk1 {
    	status = "disabled";
    };
    
    &audio_refclk0 {
    	status = "disabled";
    };
    

    I'm stil not sure why some of these things are needed, but it works.

    audio-ext-refclk1-pins-default is added to pinctrl-0 in mcasp1 to ensure that A20 is configured as DEV_BOARD0_AUDIO_EXT_REFCLK1_OUT.
    I've set the clocks 191:13 -> 191:9 and 191:19 -> 191:15 to get them linked to AUDIO_EXT_REFCLK1. k3conf sees them with the correct frequency, but for some reason /sys/kernel/debug/clk/clk_summary sees the frequency as 0.

    I've linked the AUX clock to 96 MHz (191:0 -> 191:2) and added DEV_BOARD0_AUDIO_EXT_REFCLK1_OUT as well (157:19, no parent) to ensure that clock is configured and available. I've configured the relevant frequencies as well, so that k3conf gets to see the correct frequencies.

    The simple-audio-card cpu dai needed the 12.288 MHz clock (I used 157:19 for that). This gets the simple-audio-card to set the system clock, which tells the mcasp driver to use the AHCLKR/X clocks instead of the internal AUX clock. It reads the frequency from the clock, which is the reason I had to use 157:19.

    |------------------------------------------------------------------------------|
    | VERSION INFO                                                                 |
    |------------------------------------------------------------------------------|
    | K3CONF | (version 0.3-nogit built Fri Oct 06 12:20:16 UTC 2023)              |
    | SoC    | AM62Ax SR1.0                                                        |
    | SYSFW  | ABI: 3.1 (firmware version 0x0009 '9.1.8--v09.01.08 (Kool Koala))') |
    |------------------------------------------------------------------------------|
    
    |-------------------------------------------------------------------------------------------------------------------------------------------|
    | Device ID | Clock ID | Clock Name                                                                 | Status              | Clock Frequency |
    |-------------------------------------------------------------------------------------------------------------------------------------------|
    |   157     |     0    | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN                                            | CLK_STATE_READY     | 100000000       |
    |   157     |     1    | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT      | CLK_STATE_NOT_READY | 0               |
    |   157     |     2    | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT      | CLK_STATE_READY     | 0               |
    |   157     |     3    | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT      | CLK_STATE_NOT_READY | 0               |
    |   157     |     4    | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT      | CLK_STATE_NOT_READY | 0               |
    |   157     |     5    | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT      | CLK_STATE_READY     | 0               |
    |   157     |     6    | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT      | CLK_STATE_NOT_READY | 0               |
    |   157     |     7    | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_POSTDIV1_16FFT_MAIN_1_HSDIVOUT6_CLK | CLK_STATE_READY     | 96000000        |
    |   157     |     8    | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT8_CLK  | CLK_STATE_READY     | 100000000       |
    |   157     |     9    | DEV_BOARD0_AUDIO_EXT_REFCLK0_OUT                                           | CLK_STATE_READY     | 0               |
    |   157     |    10    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN                                            | CLK_STATE_READY     | 100000000       |
    |   157     |    11    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT      | CLK_STATE_NOT_READY | 0               |
    |   157     |    12    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT      | CLK_STATE_READY     | 0               |
    |   157     |    13    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT      | CLK_STATE_NOT_READY | 0               |
    |   157     |    14    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT      | CLK_STATE_NOT_READY | 0               |
    |   157     |    15    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT      | CLK_STATE_READY     | 0               |
    |   157     |    16    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT      | CLK_STATE_NOT_READY | 0               |
    |   157     |    17    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_POSTDIV1_16FFT_MAIN_1_HSDIVOUT6_CLK | CLK_STATE_READY     | 96000000        |
    |   157     |    18    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT8_CLK  | CLK_STATE_READY     | 100000000       |
    |   157     |    19    | DEV_BOARD0_AUDIO_EXT_REFCLK1_OUT                                           | CLK_STATE_READY     | 12288000        |
    |   157     |    20    | DEV_BOARD0_CLKOUT0_IN                                                      | CLK_STATE_READY     | 50000000        |
    |   157     |    21    | DEV_BOARD0_CLKOUT0_IN_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK5            | CLK_STATE_READY     | 50000000        |
    |   157     |    22    | DEV_BOARD0_CLKOUT0_IN_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK10           | CLK_STATE_READY     | 25000000        |
    |   157     |    23    | DEV_BOARD0_CP_GEMAC_CPTS0_RFT_CLK_OUT                                      | CLK_STATE_READY     | 0               |
    |   157     |    24    | DEV_BOARD0_DDR0_CK0_IN                                                     | CLK_STATE_READY     | 250000000       |
    |   157     |    25    | DEV_BOARD0_DDR0_CK0_N_IN                                                   | CLK_STATE_READY     | 0               |
    |   157     |    27    | DEV_BOARD0_DDR0_CK0_OUT                                                    | CLK_STATE_READY     | 0               |
    |   157     |    33    | DEV_BOARD0_EXT_REFCLK1_OUT                                                 | CLK_STATE_READY     | 0               |
    |   157     |    34    | DEV_BOARD0_GPMC0_CLKLB_IN                                                  | CLK_STATE_READY     | 0               |
    |   157     |    35    | DEV_BOARD0_GPMC0_CLKLB_OUT                                                 | CLK_STATE_READY     | 0               |
    |   157     |    36    | DEV_BOARD0_GPMC0_CLK_IN                                                    | CLK_STATE_READY     | 0               |
    |   157     |    37    | DEV_BOARD0_GPMC0_FCLK_MUX_IN                                               | CLK_STATE_READY     | 133333333       |
    |   157     |    38    | DEV_BOARD0_GPMC0_FCLK_MUX_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT3_CLK      | CLK_STATE_READY     | 133333333       |
    |   157     |    39    | DEV_BOARD0_GPMC0_FCLK_MUX_IN_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT7_CLK     | CLK_STATE_READY     | 100000000       |
    |   157     |    40    | DEV_BOARD0_I2C0_SCL_IN                                                     | CLK_STATE_READY     | 0               |
    |   157     |    41    | DEV_BOARD0_I2C0_SCL_OUT                                                    | CLK_STATE_READY     | 0               |
    |   157     |    42    | DEV_BOARD0_I2C1_SCL_IN                                                     | CLK_STATE_READY     | 0               |
    |   157     |    43    | DEV_BOARD0_I2C1_SCL_OUT                                                    | CLK_STATE_READY     | 0               |
    |   157     |    44    | DEV_BOARD0_I2C2_SCL_IN                                                     | CLK_STATE_READY     | 0               |
    |   157     |    45    | DEV_BOARD0_I2C2_SCL_OUT                                                    | CLK_STATE_READY     | 0               |
    |   157     |    46    | DEV_BOARD0_I2C3_SCL_IN                                                     | CLK_STATE_READY     | 0               |
    |   157     |    47    | DEV_BOARD0_I2C3_SCL_OUT                                                    | CLK_STATE_READY     | 0               |
    |   157     |    49    | DEV_BOARD0_MCASP0_ACLKR_IN                                                 | CLK_STATE_READY     | 0               |
    |   157     |    50    | DEV_BOARD0_MCASP0_ACLKR_OUT                                                | CLK_STATE_READY     | 0               |
    |   157     |    51    | DEV_BOARD0_MCASP0_ACLKX_IN                                                 | CLK_STATE_READY     | 0               |
    |   157     |    52    | DEV_BOARD0_MCASP0_ACLKX_OUT                                                | CLK_STATE_READY     | 0               |
    |   157     |    53    | DEV_BOARD0_MCASP0_AFSR_IN                                                  | CLK_STATE_READY     | 0               |
    |   157     |    54    | DEV_BOARD0_MCASP0_AFSX_IN                                                  | CLK_STATE_READY     | 0               |
    |   157     |    55    | DEV_BOARD0_MCASP1_ACLKR_IN                                                 | CLK_STATE_READY     | 0               |
    |   157     |    56    | DEV_BOARD0_MCASP1_ACLKR_OUT                                                | CLK_STATE_READY     | 0               |
    |   157     |    57    | DEV_BOARD0_MCASP1_ACLKX_IN                                                 | CLK_STATE_READY     | 0               |
    |   157     |    58    | DEV_BOARD0_MCASP1_ACLKX_OUT                                                | CLK_STATE_READY     | 0               |
    |   157     |    59    | DEV_BOARD0_MCASP1_AFSR_IN                                                  | CLK_STATE_READY     | 0               |
    |   157     |    60    | DEV_BOARD0_MCASP1_AFSX_IN                                                  | CLK_STATE_READY     | 0               |
    |   157     |    61    | DEV_BOARD0_MCASP2_ACLKR_IN                                                 | CLK_STATE_READY     | 0               |
    |   157     |    62    | DEV_BOARD0_MCASP2_ACLKR_OUT                                                | CLK_STATE_READY     | 0               |
    |   157     |    63    | DEV_BOARD0_MCASP2_ACLKX_IN                                                 | CLK_STATE_READY     | 0               |
    |   157     |    64    | DEV_BOARD0_MCASP2_ACLKX_OUT                                                | CLK_STATE_READY     | 0               |
    |   157     |    65    | DEV_BOARD0_MCASP2_AFSR_IN                                                  | CLK_STATE_READY     | 0               |
    |   157     |    66    | DEV_BOARD0_MCASP2_AFSX_IN                                                  | CLK_STATE_READY     | 0               |
    |   157     |    67    | DEV_BOARD0_MCU_EXT_REFCLK0_OUT                                             | CLK_STATE_READY     | 0               |
    |   157     |    69    | DEV_BOARD0_MCU_I2C0_SCL_OUT                                                | CLK_STATE_READY     | 0               |
    |   157     |    70    | DEV_BOARD0_MCU_OBSCLK0_IN                                                  | CLK_STATE_READY     | 12500000        |
    |   157     |    71    | DEV_BOARD0_MCU_OBSCLK0_IN_PARENT_MCU_OBSCLK_DIV_OUT0                       | CLK_STATE_READY     | 12500000        |
    |   157     |    72    | DEV_BOARD0_MCU_OBSCLK0_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT                   | CLK_STATE_READY     | 25000000        |
    |   157     |    73    | DEV_BOARD0_MCU_SPI0_CLK_IN                                                 | CLK_STATE_READY     | 0               |
    |   157     |    74    | DEV_BOARD0_MCU_SPI0_CLK_OUT                                                | CLK_STATE_READY     | 0               |
    |   157     |    75    | DEV_BOARD0_MCU_SPI1_CLK_IN                                                 | CLK_STATE_READY     | 0               |
    |   157     |    76    | DEV_BOARD0_MCU_SPI1_CLK_OUT                                                | CLK_STATE_READY     | 0               |
    |   157     |    77    | DEV_BOARD0_MCU_SYSCLKOUT0_IN                                               | CLK_STATE_READY     | 100000000       |
    |   157     |    78    | DEV_BOARD0_MCU_TIMER_IO0_IN                                                | CLK_STATE_READY     | 0               |
    |   157     |    79    | DEV_BOARD0_MCU_TIMER_IO1_IN                                                | CLK_STATE_READY     | 0               |
    |   157     |    80    | DEV_BOARD0_MCU_TIMER_IO2_IN                                                | CLK_STATE_READY     | 0               |
    |   157     |    81    | DEV_BOARD0_MCU_TIMER_IO3_IN                                                | CLK_STATE_READY     | 0               |
    |   157     |    82    | DEV_BOARD0_MDIO0_MDC_IN                                                    | CLK_STATE_READY     | 0               |
    |   157     |    83    | DEV_BOARD0_MMC0_CLKLB_IN                                                   | CLK_STATE_READY     | 0               |
    |   157     |    84    | DEV_BOARD0_MMC0_CLKLB_OUT                                                  | CLK_STATE_READY     | 0               |
    |   157     |    85    | DEV_BOARD0_MMC0_CLK_IN                                                     | CLK_STATE_READY     | 0               |
    |   157     |    86    | DEV_BOARD0_MMC0_CLK_OUT                                                    | CLK_STATE_READY     | 0               |
    |   157     |    87    | DEV_BOARD0_MMC1_CLKLB_IN                                                   | CLK_STATE_READY     | 0               |
    |   157     |    88    | DEV_BOARD0_MMC1_CLKLB_OUT                                                  | CLK_STATE_READY     | 0               |
    |   157     |    89    | DEV_BOARD0_MMC1_CLK_IN                                                     | CLK_STATE_READY     | 0               |
    |   157     |    90    | DEV_BOARD0_MMC1_CLK_OUT                                                    | CLK_STATE_READY     | 0               |
    |   157     |    91    | DEV_BOARD0_MMC2_CLKLB_IN                                                   | CLK_STATE_READY     | 0               |
    |   157     |    92    | DEV_BOARD0_MMC2_CLKLB_OUT                                                  | CLK_STATE_READY     | 0               |
    |   157     |    93    | DEV_BOARD0_MMC2_CLK_IN                                                     | CLK_STATE_READY     | 0               |
    |   157     |    94    | DEV_BOARD0_MMC2_CLK_OUT                                                    | CLK_STATE_READY     | 0               |
    |   157     |    95    | DEV_BOARD0_OBSCLK0_IN                                                      | CLK_STATE_READY     | 500000000       |
    |   157     |    96    | DEV_BOARD0_OBSCLK0_IN_PARENT_MAIN_OBSCLK_DIV_OUT0                          | CLK_STATE_READY     | 500000000       |
    |   157     |    97    | DEV_BOARD0_OBSCLK0_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT                       | CLK_STATE_READY     | 25000000        |
    |   157     |   128    | DEV_BOARD0_OBSCLK1_IN                                                      | CLK_STATE_READY     | 500000000       |
    |   157     |   129    | DEV_BOARD0_OSPI0_DQS_OUT                                                   | CLK_STATE_READY     | 0               |
    |   157     |   130    | DEV_BOARD0_OSPI0_LBCLKO_IN                                                 | CLK_STATE_READY     | 0               |
    |   157     |   131    | DEV_BOARD0_OSPI0_LBCLKO_OUT                                                | CLK_STATE_READY     | 0               |
    |   157     |   132    | DEV_BOARD0_RGMII1_RXC_OUT                                                  | CLK_STATE_READY     | 0               |
    |   157     |   133    | DEV_BOARD0_RGMII1_TXC_IN                                                   | CLK_STATE_READY     | 0               |
    |   157     |   134    | DEV_BOARD0_RGMII1_TXC_OUT                                                  | CLK_STATE_READY     | 0               |
    |   157     |   135    | DEV_BOARD0_RGMII2_RXC_OUT                                                  | CLK_STATE_READY     | 0               |
    |   157     |   136    | DEV_BOARD0_RGMII2_TXC_IN                                                   | CLK_STATE_READY     | 0               |
    |   157     |   137    | DEV_BOARD0_RGMII2_TXC_OUT                                                  | CLK_STATE_READY     | 0               |
    |   157     |   138    | DEV_BOARD0_RMII1_REF_CLK_OUT                                               | CLK_STATE_READY     | 0               |
    |   157     |   139    | DEV_BOARD0_RMII2_REF_CLK_OUT                                               | CLK_STATE_READY     | 0               |
    |   157     |   140    | DEV_BOARD0_SPI0_CLK_IN                                                     | CLK_STATE_READY     | 0               |
    |   157     |   141    | DEV_BOARD0_SPI0_CLK_OUT                                                    | CLK_STATE_READY     | 0               |
    |   157     |   142    | DEV_BOARD0_SPI1_CLK_IN                                                     | CLK_STATE_READY     | 0               |
    |   157     |   143    | DEV_BOARD0_SPI1_CLK_OUT                                                    | CLK_STATE_READY     | 0               |
    |   157     |   144    | DEV_BOARD0_SPI2_CLK_IN                                                     | CLK_STATE_READY     | 0               |
    |   157     |   145    | DEV_BOARD0_SPI2_CLK_OUT                                                    | CLK_STATE_READY     | 0               |
    |   157     |   146    | DEV_BOARD0_SYSCLKOUT0_IN                                                   | CLK_STATE_READY     | 125000000       |
    |   157     |   147    | DEV_BOARD0_TCK_OUT                                                         | CLK_STATE_READY     | 0               |
    |   157     |   148    | DEV_BOARD0_TIMER_IO0_IN                                                    | CLK_STATE_READY     | 0               |
    |   157     |   149    | DEV_BOARD0_TIMER_IO1_IN                                                    | CLK_STATE_READY     | 0               |
    |   157     |   150    | DEV_BOARD0_TIMER_IO2_IN                                                    | CLK_STATE_READY     | 0               |
    |   157     |   151    | DEV_BOARD0_TIMER_IO3_IN                                                    | CLK_STATE_READY     | 0               |
    |   157     |   152    | DEV_BOARD0_TIMER_IO4_IN                                                    | CLK_STATE_READY     | 0               |
    |   157     |   153    | DEV_BOARD0_TIMER_IO5_IN                                                    | CLK_STATE_READY     | 0               |
    |   157     |   154    | DEV_BOARD0_TIMER_IO6_IN                                                    | CLK_STATE_READY     | 0               |
    |   157     |   155    | DEV_BOARD0_TIMER_IO7_IN                                                    | CLK_STATE_READY     | 0               |
    |   157     |   156    | DEV_BOARD0_TRC_CLK_IN                                                      | CLK_STATE_READY     | 0               |
    |   157     |   157    | DEV_BOARD0_VOUT0_EXTPCLKIN_OUT                                             | CLK_STATE_READY     | 0               |
    |   157     |   158    | DEV_BOARD0_VOUT0_PCLK_IN                                                   | CLK_STATE_READY     | 0               |
    |   157     |   159    | DEV_BOARD0_WKUP_CLKOUT0_IN                                                 | CLK_STATE_NOT_READY | 0               |
    |   157     |   160    | DEV_BOARD0_WKUP_CLKOUT0_IN_PARENT_WKUP_CLKOUT_SEL_OUT0                     | CLK_STATE_NOT_READY | 0               |
    |   157     |   161    | DEV_BOARD0_WKUP_CLKOUT0_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT                  | CLK_STATE_READY     | 25000000        |
    |-------------------------------------------------------------------------------------------------------------------------------------------|
    
    |------------------------------------------------------------------------------|
    | VERSION INFO                                                                 |
    |------------------------------------------------------------------------------|
    | K3CONF | (version 0.3-nogit built Fri Oct 06 12:20:16 UTC 2023)              |
    | SoC    | AM62Ax SR1.0                                                        |
    | SYSFW  | ABI: 3.1 (firmware version 0x0009 '9.1.8--v09.01.08 (Kool Koala))') |
    |------------------------------------------------------------------------------|
    
    |-----------------------------------------------------------------------------------------------------------------------------|
    | Device ID | Clock ID | Clock Name                                                       | Status          | Clock Frequency |
    |-----------------------------------------------------------------------------------------------------------------------------|
    |   191     |     0    | DEV_MCASP1_AUX_CLK                                               | CLK_STATE_READY | 96000000        |
    |   191     |     1    | DEV_MCASP1_AUX_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT8_CLK     | CLK_STATE_READY | 100000000       |
    |   191     |     2    | DEV_MCASP1_AUX_CLK_PARENT_POSTDIV1_16FFT_MAIN_1_HSDIVOUT6_CLK    | CLK_STATE_READY | 96000000        |
    |   191     |     3    | DEV_MCASP1_MCASP_ACLKR_PIN                                       | CLK_STATE_READY | 0               |
    |   191     |     4    | DEV_MCASP1_MCASP_ACLKR_POUT                                      | CLK_STATE_READY | 0               |
    |   191     |     5    | DEV_MCASP1_MCASP_ACLKX_PIN                                       | CLK_STATE_READY | 0               |
    |   191     |     6    | DEV_MCASP1_MCASP_ACLKX_POUT                                      | CLK_STATE_READY | 0               |
    |   191     |     7    | DEV_MCASP1_MCASP_AFSR_POUT                                       | CLK_STATE_READY | 0               |
    |   191     |     8    | DEV_MCASP1_MCASP_AFSX_POUT                                       | CLK_STATE_READY | 0               |
    |   191     |     9    | DEV_MCASP1_MCASP_AHCLKR_PIN                                      | CLK_STATE_READY | 12288000        |
    |   191     |    10    | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_EXT_REFCLK1_OUT       | CLK_STATE_READY | 0               |
    |   191     |    11    | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT       | CLK_STATE_READY | 25000000        |
    |   191     |    12    | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT | CLK_STATE_READY | 0               |
    |   191     |    13    | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT | CLK_STATE_READY | 12288000        |
    |   191     |    14    | DEV_MCASP1_MCASP_AHCLKR_POUT                                     | CLK_STATE_READY | 0               |
    |   191     |    15    | DEV_MCASP1_MCASP_AHCLKX_PIN                                      | CLK_STATE_READY | 12288000        |
    |   191     |    16    | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_EXT_REFCLK1_OUT       | CLK_STATE_READY | 0               |
    |   191     |    17    | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT       | CLK_STATE_READY | 25000000        |
    |   191     |    18    | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT | CLK_STATE_READY | 0               |
    |   191     |    19    | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT | CLK_STATE_READY | 12288000        |
    |   191     |    20    | DEV_MCASP1_MCASP_AHCLKX_POUT                                     | CLK_STATE_READY | 0               |
    |   191     |    21    | DEV_MCASP1_VBUSP_CLK                                             | CLK_STATE_READY | 250000000       |
    |-----------------------------------------------------------------------------------------------------------------------------|
    
    |------------------------------------------------------------------------------|
    | VERSION INFO                                                                 |
    |------------------------------------------------------------------------------|
    | K3CONF | (version 0.3-nogit built Fri Oct 06 12:20:16 UTC 2023)              |
    | SoC    | AM62Ax SR1.0                                                        |
    | SYSFW  | ABI: 3.1 (firmware version 0x0009 '9.1.8--v09.01.08 (Kool Koala))') |
    |------------------------------------------------------------------------------|
    
    |-------------------------------------------------|
    | Device ID | Device Name       | Device Status   |
    |-------------------------------------------------|
    |   191     | AM62AX_DEV_MCASP1 | DEVICE_STATE_ON |
    |-------------------------------------------------|
    
    Linux clks:
                                     enable  prepare  protect                                duty  hardware
       clock                          count    count    count        rate   accuracy phase  cycle    enable
    -------------------------------------------------------------------------------------------------------
     clk:204:2                            1        1        0   400000000          0     0  50000         Y
     clk:201:0                            0        0        0   250000000          0     0  50000         Y
     clk:191:19                           0        0        0           0          0     0  50000         Y
        clk:191:15                        0        0        0           0          0     0  50000         Y
     clk:191:18                           0        0        0           0          0     0  50000         Y
     clk:191:17                           0        0        0    25000000          0     0  50000         Y
     clk:191:16                           0        0        0           0          0     0  50000         Y
     clk:191:13                           0        0        0           0          0     0  50000         Y
        clk:191:9                         0        0        0           0          0     0  50000         Y
     clk:191:12                           0        0        0           0          0     0  50000         Y
     clk:191:11                           0        0        0    25000000          0     0  50000         Y
     clk:191:10                           0        0        0           0          0     0  50000         Y
     clk:191:2                            0        0        0    96000000          0     0  50000         Y
        clk:191:0                         0        0        0    96000000          0     0  50000         Y
     clk:191:1                            0        0        0   100000000          0     0  50000         Y
     clk:189:6                            0        0        0   200000000          0     0  50000         Y
     clk:189:5                            0        0        0    25000000          0     0  50000         Y
     clk:189:4                            0        0        0    25000000          0     0  50000         Y
     clk:189:3                            0        0        0           0          0     0  50000         Y
     clk:189:2                            0        0        0    20000000          0     0  50000         Y
        clk:189:1                         0        0        0    20000000          0     0  50000         Y
     clk:188:6                            0        0        0   200000000          0     0  50000         Y
     clk:188:5                            0        0        0    25000000          0     0  50000         Y
     clk:188:4                            0        0        0    25000000          0     0  50000         Y
     clk:188:3                            0        0        0           0          0     0  50000         Y
     clk:188:2                            0        0        0    20000000          0     0  50000         Y
        clk:188:1                         0        0        0    20000000          0     0  50000         Y
     clk:186:6                            0        0        0   250000000          0     0  50000         Y
     clk:186:4                            0        0        0           0          0     0  50000         Y
     clk:186:3                            0        0        0   170000000          0     0  50000         Y
        clk:186:2                         0        0        0   170000000          0     0  50000         Y
     clk:186:0                            0        0        0   170000000          0     0  50000         Y
     clk:182:4                            0        0        0   375000000          0     0  50000         Y
     clk:182:3                            0        0        0   250000000          0     0  50000         Y
     clk:182:0                            0        0        0   500000000          0     0  50000         Y
     clk:162:5                            0        0        0    50000000          0     0  50000         Y
     clk:162:4                            1        1        0    25000000          0     0  50000         Y
        clk:162:3                         1        1        0    25000000          0     0  50000         Y
     clk:161:5                            0        0        0    50000000          0     0  50000         Y
     clk:161:4                            1        1        0    25000000          0     0  50000         Y
        clk:161:3                         1        1        0    25000000          0     0  50000         Y
     clk:157:19                           1        1        0    12288000          0     0  50000         Y
     clk:149:0                            0        0        0    48000000          0     0  50000         Y
     clk:146:2                            0        0        0   160000000          0     0  50000         Y
     clk:146:1                            0        0        0    48000000          0     0  50000         Y
        clk:146:0                         0        0        0    48000000          0     0  50000         Y
     clk:138:0                            0        0        0  1200000000          0     0  50000         Y
     clk:137:0                            0        0        0  1200000000          0     0  50000         Y
     clk:136:0                            0        0        0  1200000000          0     0  50000         Y
     clk:135:0                            0        0        0  1250000000          0     0  50000         Y
     clk:117:8                            0        0        0    50000000          0     0  50000         Y
     clk:117:7                            1        1        0    50000000          0     0  50000         Y
        clk:117:6                         1        1        0    50000000          0     0  50000         Y
     clk:117:2                            0        0        0       32552          0     0  50000         Y
     clk:117:1                            1        1        0       32552          0     0  50000         Y
        clk:117:0                         1        1        0       32552          0     0  50000         Y
     clk:104:2                            0        0        0    96000000          0     0  50000         Y
     clk:103:2                            0        0        0    96000000          0     0  50000         Y
     clk:102:2                            0        0        0    96000000          0     0  50000         Y
     clk:79:4                             0        0        0     3125000          0     0  50000         Y
     clk:79:3                             0        0        0        8138          0     0  50000         Y
     clk:79:2                             0        0        0           0          0     0  50000         Y
     clk:79:1                             1        1        0    25000000          0     0  50000         Y
        clk:79:0                          1        1        0    25000000          0     0  50000         Y
     clk:78:0                             1        1        0   125000000          0     0  50000         Y
     clk:77:0                             1        1        0   125000000          0     0  50000         Y
     clk:75:9                             0        0        0   160000000          0     0  50000         Y
     clk:75:8                             0        0        0   200000000          0     0  50000         Y
        clk:75:7                          0        0        0   166666666          0     0  50000         Y
     clk:58:8                             1        1        0   200000000          0     0  50000         Y
        clk:58:6                          1        1        0   200000000          0     0  50000         Y
     clk:58:7                             0        0        0   200000000          0     0  50000         Y
     clk:58:5                             0        0        0   250000000          0     0  50000         Y
     clk:57:8                             1        1        0   200000000          0     0  50000         Y
        clk:57:6                          1        1        0   200000000          0     0  50000         Y
     clk:57:7                             0        0        0   200000000          0     0  50000         Y
     clk:57:5                             0        0        0   250000000          0     0  50000         Y
     clk:43:4                             0        0        0           0          0     0  50000         Y
     clk:43:3                             0        0        0    25000000          0     0  50000         Y
        clk:43:2                          0        0        0    25000000          0     0  50000         Y
     clk:42:18                            0        0        0           0          0     0  50000         Y
     clk:42:17                            0        0        0           0          0     0  50000         Y
     clk:42:16                            0        0        0           0          0     0  50000         Y
     clk:42:15                            0        0        0   187500000          0     0  50000         Y
     clk:42:14                            0        0        0           0          0     0  50000         Y
     clk:42:13                            0        0        0           0          0     0  50000         Y
     clk:42:12                            0        0        0   250000000          0     0  50000         Y
     clk:42:11                            0        0        0   192000000          0     0  50000         Y
     clk:42:10                            0        0        0           0          0     0  50000         Y
     clk:42:9                             0        0        0           0          0     0  50000         Y
     clk:42:8                             0        0        0           0          0     0  50000         Y
     clk:42:7                             0        0        0           0          0     0  50000         Y
     clk:42:6                             0        0        0    12500000          0     0  50000         Y
     clk:42:5                             0        0        0   200000000          0     0  50000         Y
     clk:42:4                             0        0        0       32552          0     0  50000         Y
     clk:42:3                             0        0        0    25000000          0     0  50000         Y
        clk:42:2                          0        0        0    25000000          0     0  50000         Y
     clk:41:4                             0        0        0           0          0     0  50000         Y
     clk:41:3                             0        0        0    25000000          0     0  50000         Y
        clk:41:2                          0        0        0    25000000          0     0  50000         Y
     clk:40:18                            0        0        0           0          0     0  50000         Y
     clk:40:17                            0        0        0           0          0     0  50000         Y
     clk:40:16                            0        0        0           0          0     0  50000         Y
     clk:40:15                            0        0        0   187500000          0     0  50000         Y
     clk:40:14                            0        0        0           0          0     0  50000         Y
     clk:40:13                            0        0        0           0          0     0  50000         Y
     clk:40:12                            0        0        0   250000000          0     0  50000         Y
     clk:40:11                            0        0        0   192000000          0     0  50000         Y
     clk:40:10                            0        0        0           0          0     0  50000         Y
     clk:40:9                             0        0        0           0          0     0  50000         Y
     clk:40:8                             0        0        0           0          0     0  50000         Y
     clk:40:7                             0        0        0           0          0     0  50000         Y
     clk:40:6                             0        0        0    12500000          0     0  50000         Y
     clk:40:5                             0        0        0   200000000          0     0  50000         Y
     clk:40:4                             0        0        0       32552          0     0  50000         Y
     clk:40:3                             0        0        0    25000000          0     0  50000         Y
        clk:40:2                          0        0        0    25000000          0     0  50000         Y
     clk:39:4                             0        0        0           0          0     0  50000         Y
     clk:39:3                             0        0        0    25000000          0     0  50000         Y
        clk:39:2                          0        0        0    25000000          0     0  50000         Y
     clk:38:18                            0        0        0           0          0     0  50000         Y
     clk:38:17                            0        0        0           0          0     0  50000         Y
     clk:38:16                            0        0        0           0          0     0  50000         Y
     clk:38:15                            0        0        0   187500000          0     0  50000         Y
     clk:38:14                            0        0        0           0          0     0  50000         Y
     clk:38:13                            0        0        0           0          0     0  50000         Y
     clk:38:12                            0        0        0   250000000          0     0  50000         Y
     clk:38:11                            0        0        0   192000000          0     0  50000         Y
     clk:38:10                            0        0        0           0          0     0  50000         Y
     clk:38:9                             0        0        0           0          0     0  50000         Y
     clk:38:8                             0        0        0           0          0     0  50000         Y
     clk:38:7                             0        0        0           0          0     0  50000         Y
     clk:38:6                             0        0        0    12500000          0     0  50000         Y
     clk:38:5                             0        0        0   200000000          0     0  50000         Y
     clk:38:4                             0        0        0       32552          0     0  50000         Y
     clk:38:3                             0        0        0    25000000          0     0  50000         Y
        clk:38:2                          0        0        0    25000000          0     0  50000         Y
     clk:37:4                             0        0        0           0          0     0  50000         Y
     clk:37:3                             0        0        0    25000000          0     0  50000         Y
        clk:37:2                          0        0        0    25000000          0     0  50000         Y
     clk:36:18                            0        0        0           0          0     0  50000         Y
     clk:36:17                            0        0        0           0          0     0  50000         Y
     clk:36:16                            0        0        0           0          0     0  50000         Y
     clk:36:15                            0        0        0   187500000          0     0  50000         Y
     clk:36:14                            0        0        0           0          0     0  50000         Y
     clk:36:13                            0        0        0           0          0     0  50000         Y
     clk:36:12                            0        0        0   250000000          0     0  50000         Y
     clk:36:11                            0        0        0   192000000          0     0  50000         Y
     clk:36:10                            0        0        0           0          0     0  50000         Y
     clk:36:9                             0        0        0           0          0     0  50000         Y
     clk:36:8                             0        0        0           0          0     0  50000         Y
     clk:36:7                             0        0        0           0          0     0  50000         Y
     clk:36:6                             0        0        0    12500000          0     0  50000         Y
     clk:36:5                             0        0        0   200000000          0     0  50000         Y
     clk:36:4                             0        0        0       32552          0     0  50000         Y
     clk:36:3                             0        0        0    25000000          0     0  50000         Y
        clk:36:2                          0        0        0    25000000          0     0  50000         Y
     clk:13:11                            1        1        0   500000000          0     0  50000         Y
        clk:13:3                          1        1        0   500000000          0     0  50000         Y
     clk:13:10                            0        0        0   400000000          0     0  50000         Y
     clk:13:9                             0        0        0           0          0     0  50000         Y
     clk:13:8                             0        0        0           0          0     0  50000         Y
     clk:13:7                             0        0        0           0          0     0  50000         Y
     clk:13:6                             0        0        0           0          0     0  50000         Y
     clk:13:5                             0        0        0   200000000          0     0  50000         Y
     clk:13:4                             0        0        0   500000000          0     0  50000         Y
     clk:13:0                             0        0        0   250000000          0     0  50000         Y
     epwm_tbclk2                          0        0        0           0          0     0  50000         N
     epwm_tbclk1                          0        0        0           0          0     0  50000         N
     epwm_tbclk0                          0        0        0           0          0     0  50000         N
     imx219-xclk                          0        0        0    24000000          0     0  50000         Y
    McASP1 registers: 
    Read at address  0x02B10000 (0xffffbca20000): 0x44307B02
    Read at address  0x02B10004 (0xffffa2851004): 0x00000002
    Read at address  0x02B10010 (0xffffa9731010): 0x00000000
    Read at address  0x02B10014 (0xffff8288e014): 0xB4000000
    Read at address  0x02B10018 (0xffff94164018): 0x00000000
    Read at address  0x02B1001C (0xffff91df301c): 0x48000000
    Read at address  0x02B10020 (0xffff89072020): 0x00000000
    Read at address  0x02B10044 (0xffff95455044): 0x0000131F
    Read at address  0x02B10048 (0xffff8cf16048): 0x00000000
    Read at address  0x02B1004C (0xffffabfa304c): 0x00000000
    Read at address  0x02B10050 (0xffff84cee050): 0x00000000
    Read at address  0x02B10060 (0xffff8f6fe060): 0x0000131F
    Read at address  0x02B10064 (0xffffbceb1064): 0xFFFFFFFF
    Read at address  0x02B10068 (0xffff9af9a068): 0x000180F0
    Read at address  0x02B1006C (0xffff8aa1506c): 0x00000113
    Read at address  0x02B10070 (0xffff93ee0070): 0x000000A3
    Read at address  0x02B10074 (0xffff9a642074): 0x00000000
    Read at address  0x02B10078 (0xffffaec9f078): 0x00000003
    Read at address  0x02B1007C (0xffffb368c07c): 0x00000001
    Read at address  0x02B10080 (0xffff82686080): 0x00000154
    Read at address  0x02B10084 (0xffffb1e03084): 0x00000001
    Read at address  0x02B10088 (0xffffb7b21088): 0x8A000000
    Read at address  0x02B1008C (0xffff870c608c): 0x00000000
    Read at address  0x02B100A0 (0xffff9f6210a0): 0x0000131F
    Read at address  0x02B100A4 (0xffffaedda0a4): 0xFFFFFFFF
    Read at address  0x02B100A8 (0xffff985f70a8): 0x000100F0
    Read at address  0x02B100AC (0xffff8e31b0ac): 0x00000113
    Read at address  0x02B100B0 (0xffffb0a7d0b0): 0x000000A3
    Read at address  0x02B100B4 (0xffffa8ae40b4): 0x00000000
    Read at address  0x02B100B8 (0xffffbcf090b8): 0x00000000
    Read at address  0x02B100BC (0xffffb2ab30bc): 0x00000000
    Read at address  0x02B100C0 (0xffff9346d0c0): 0x0000010C
    Read at address  0x02B100C4 (0xffff826a20c4): 0x0000017F
    Read at address  0x02B100C8 (0xffffb8fd80c8): 0x8A000000
    Read at address  0x02B100CC (0xffffbd55e0cc): 0x00000000
    Read at address  0x02B10100 (0xffffa2cf8100): 0x00000000
    Read at address  0x02B10104 (0xffff90bd1104): 0x00000000
    Read at address  0x02B10108 (0xffff9a1aa108): 0x00000000
    Read at address  0x02B1010C (0xffffb12da10c): 0x00000000
    Read at address  0x02B10110 (0xffff865e5110): 0x00000000
    Read at address  0x02B10114 (0xffffba043114): 0x00000000
    Read at address  0x02B10118 (0xffffbc856118): 0x00000000
    Read at address  0x02B1011C (0xffffa942e11c): 0x00000000
    Read at address  0x02B10120 (0xffffad4aa120): 0x00000000
    Read at address  0x02B10124 (0xffffae6df124): 0x00000000
    Read at address  0x02B10128 (0xffffa6eac128): 0x00000000
    Read at address  0x02B1012C (0xffff9ddbf12c): 0x00000000
    Read at address  0x02B10130 (0xffff8236a130): 0x00000000
    Read at address  0x02B10134 (0xffffaccea134): 0x00000000
    Read at address  0x02B10138 (0xffffb196d138): 0x00000000
    Read at address  0x02B1013C (0xffffa064d13c): 0x00000000
    Read at address  0x02B10140 (0xffffb84e1140): 0x00000000
    Read at address  0x02B10144 (0xffff9923e144): 0x00000000
    Read at address  0x02B10148 (0xffffb0001148): 0x00000000
    Read at address  0x02B1014C (0xffffa16f414c): 0x00000000
    Read at address  0x02B10150 (0xffff87084150): 0x00000000
    Read at address  0x02B10154 (0xffff877ec154): 0x00000000
    Read at address  0x02B10158 (0xffffb7b9f158): 0x00000000
    Read at address  0x02B1015C (0xffffb621e15c): 0x00000000
    Read at address  0x02B10180 (0xffffbad22180): 0x00000008
    Read at address  0x02B10184 (0xffffaff14184): 0x00000000
    Read at address  0x02B10188 (0xffffb9a9a188): 0x00000002
    Read at address  0x02B1018C (0xffffbdc1618c): 0x00000000
    Read at address  0x02B10190 (0xffff80d13190): 0x00000000
    Read at address  0x02B10194 (0xffffb8aea194): 0x00000000
    Read at address  0x02B10198 (0xffffa5fc6198): 0x00000000
    Read at address  0x02B1019C (0xffff8aa3219c): 0x00000000
    Read at address  0x02B101A0 (0xffff87f221a0): 0x00000000
    Read at address  0x02B101A4 (0xffff9ca4b1a4): 0x00000000
    Read at address  0x02B101A8 (0xffffb401e1a8): 0x00000000
    Read at address  0x02B101AC (0xffffb11501ac): 0x00000000
    Read at address  0x02B101B0 (0xffff958bd1b0): 0x00000000
    Read at address  0x02B101B4 (0xffffaf7d31b4): 0x00000000
    Read at address  0x02B101B8 (0xffff94c361b8): 0x00000000
    Read at address  0x02B101BC (0xffff9e4bc1bc): 0x00000000
    Read at address  0x02B11000 (0xffffb766c000): 0x00007B02
    Read at address  0x02B11004 (0xffff80c96004): 0x00000000
    Read at address  0x02B11008 (0xffffaf4cf008): 0x00012001
    Read at address  0x02B1100C (0xffffb604600c): 0x0000001A
    

    Regards,

    Bas Vermeulen

  • Hi Bas,

    Thanks for sharing the DTS file for the community to use. I am glad you were able to resolve the issue. As, we in our SDK offering, use Codec as the master driving the clock, this will definitely help the community, wanting the SoC to providing MCLK for their devices connected. 

    I am going to close this thread. Feel, free to reach out for any further assistance.

    Best Regards,

    Suren

  • Hi Suren,

    I would be interested to know how to get the linux clock system to see the clock frequencies that I set with assigned-clock-rates in the device tree.

    That's the one thing I haven't found out yet. If you happen to know, that would be helpful.

    Regards,

    Bas 

  • Bas,

    Please refer the documentation on clock bindings in Linux kernel. 

    https://github.com/devicetree-org/dt-schema/blob/main/dtschema/schemas/clock/clock.yaml

    Best Regards,

    Suren

  • Hi Suren,

    I set the clock rates in my device tree overlay, but those don't get propagated to the linux clock system. They're correct in k3conf, but /sys/kernel/debug/clk/clk_summary shows 0 instead of the 12288000 I set in my device tree overlay.

    That causes some problems when I use the actual clock in the simple-audio-card definition (sees a frequency of 0, and switches to a different clock because of it). That's why I'm using clock 157:19 there instead of clock 191:9. I'm not sure how those settings are propagated, possibly I can't set the rate for 191:9 and 191:15 because the parents rates aren't set.

    Regards,

    Bas Vermeulen

  • Hi Bas,

    Would removing the extra parameter for audio_ext_refclk1 in clocks, assigned-clocks and assigned-clock-rates help?

    	clock-names = "ahclkr", "ahclkx", "fck", "audio_ext_refclk1";
    	clocks = <&k3_clks 191 9>, <&k3_clks 191 15>, <&k3_clks 191 0>, <&k3_clks 157 19>;
    	assigned-clocks = <&k3_clks 191 9>, <&k3_clks 191 15>, <&k3_clks 191 0>, <&k3_clks 157 19>;
    	assigned-clock-parents = <&k3_clks 191 13>, <&k3_clks 191 19>, <&k3_clks 191 2>;
    	assigned-clock-rates = <12288000>, <12288000>, <96000000>, <12288000>;

    Also please refer to AM62Ax clock identifiers for exact mapping here: https://software-dl.ti.com/tisci/esd/latest/5_soc_doc/am62ax/clocks.html

    Hope this helps

    Best Regards,

    Suren

  • Hi Suren,

    I need the <&k3_clks 157 19> to be able to set the clock rate for DEV_BOARD0_AUDIO_EXT_REFCLK1_OUT. That's how I tell the system that DEV_BOARD0_AUDIO_EXT_REFCLK1_OUT is a 12.288 MHz clock. I can't use the audio_refclk1 device, since that needs a clock parent (it's intended to be used for DEV_BOARD0_AUDIO_EXT_REFCLKx_IN, to specify what parent clock to use for that).

    I'm aware of the exact mappings, I just haven't managed to figure out how the various rates propagate through the system yet. In here I set the clock rates for 191:9 and 191:15, but I'm guessing the system doesn't know to propagate the 12.288 MHz clock rate from 157:19 to 191:13 and 191:19 that are used as parents for 191:9 and 191:15. Because the parent rates are 0, the 12.288 MHz I set here doesn't take in the linux clock tree.

    I'm just not sure how to define it correctly. Can I use a fixed-clock to define the clock rate for 157:19 by using assigned-clock-rate to set the frequency? And do I have to do the same for 191:9 and 191:15? Or is there a way to have this propagate automatically?

    Regards,

    Bas Vermeulen