Booting from paralell FLASH takes way to long...

Which chip select is the NOR flash using? Are you using RTC clock source or external clock source?

The C5515/C5505 DSP bootloader has a fixed order in which it checks for a valid boot-image in each external memory until it locates a valid boot image.

NOR flash is the first class of memories checked by the bootloader.

The order or chip selects checked is EM_CS2, then EM_CS3, EM_CS4, EM_CS5.

So if your NOR flash is connected to EM_CS2, then it is the first device checked and the bootloader is not delaying boot by checking other chip selects.

During bootloader from NOR flash, the system clock runs at ~12MHz

If CLK_SEL = 0, RTC CLK (32768Hz) is multiplied by 375 to create 12.288MHz

If CLK_SEL = 1, External Crystal clock is bypassed to the SYSCLK (12 MHz is recommended)

For NOR boot you can experiment with faster external crystals and CLK_SEL = 1 to see improvement in the boot speed.

External clock input of up to 100 MHz is supported, but with this clock booting from other memories will fail because the dividers are based on 12.288MHz (I2C, SPI, UART, USB)

See the C5515/05 Bootloader Appnote: http://focus.ti.com/lit/an/sprabd7/sprabd7.pdf

Hope this helps,
Mark

Mark,

We still uses the 5509A DSP.

According to SPRA375F this DSP boots from CS_1 first. We for FLASH on CS_1 and SRAM on CS_2, and FPGA on CS_3.

We se aprox. 3 sec. boot time with 256KB code, after we have set what we belive is the right values in the EMIF CONFIG registers using using the CMD file.

/* Set the Emif mode to full emif...                                                                   */

-reg_config  0x6C00,0x0201

/* Set chip select 0 paramters...                                                                      */
-reg_config  0x0806,0x1002
-reg_config  0x0807,0x5002

/* Set chip select 1 paramters...                                                                      */
-reg_config  0x0809,0x1002
-reg_config  0x080a,0x5002

/* Set production parameters, not used, does not matter...                                             */
-reg_config  0x07FE,0x0510
-reg_config  0x07FF,0x0000

/* After register settings is applied, we need a short delay, min 10MSYCLE, the parameter is MSYCLE... */
-delay 0x200

Terje